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ChipTest/PAN159/PAN159-Template/SampleCode/Template/Keil/obj/debug.o
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外设驱动改为库，减少编译时间
2021-10-07 09:32:05 +08:00
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..\debug\debug.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] D:\WORK\Guitar\ChipTest\PAN159\PAN159-Template\SampleCode\Template\Keil<..\debug\debug.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] D:\WORK\Guitar\ChipTest\PAN159\PAN159-Template\SampleCode\Template\Keil2>» dbg_update:2^__result:P0Yindex:N‹:"˜ Yfunc‘hZrf_bak_mode:!d..\debug\debug.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] D:\WORK\Guitar\ChipTest\PAN159\PAN159-Template\SampleCode\Template\Keil2>å0 __dbg_data_up_00:2^__result:P.*»len:#mid:#Ÿ:dat#datend:#*Ëströ#Zi:9Yframe;‘`ˆ..\debug\debug.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] D:\WORK\Guitar\ChipTest\PAN159\PAN159-Template\SampleCode\Template\Keil6>‰J __dbg_data_up_0:6^__result:P2*ªlen:#mid:#ž
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PXGS_BUF_TYPE uint8_t PXGS_LEN_TYPE uint8_t PXGS_MID_TYPE uint8_t
PXGS_SID_TYPE uint8_tPXGS_CHK_TYPE uint8_tPXGS_STATIC_INLINE static __inlinePXGS_MID_HAS_SID(MID) (((MID)&0xF0)==0xF0)2PXGS_U_MID_PLOT_00 0x003PXGS_U_MID_PLOT_00_DATA_TYPE int16_t4PXGS_U_MID_PLOT_00_DATA_ENLARGE 1005PXGS_U_MID_PLOT_00_DATA_PACK(DATA) (PXGS_U_MID_PLOT_00_DATA_ENLARGE*(DATA))>PXGS_U_MID_PLOT_01 0x01?PXGS_U_MID_PLOT_01_DATA_TYPE int16_t@PXGS_U_MID_PLOT_01_DATA_ENLARGE 100APXGS_U_MID_PLOT_01_DATA_PACK(DATA) (PXGS_U_MID_PLOT_01_DATA_ENLARGE*(DATA))JPXGS_U_MID_PLOT_02 0x02KPXGS_U_MID_PLOT_02_DATA_TYPE int16_tLPXGS_U_MID_PLOT_02_DATA_ENLARGE 100MPXGS_U_MID_PLOT_02_DATA_PACK(DATA) (PXGS_U_MID_PLOT_02_DATA_ENLARGE*(DATA))VPXGS_U_MID_PLOT_03 0x03WPXGS_U_MID_PLOT_03_DATA_TYPE int16_tXPXGS_U_MID_PLOT_03_DATA_ENLARGE 10YPXGS_U_MID_PLOT_03_DATA_PACK(DATA) (PXGS_U_MID_PLOT_03_DATA_ENLARGE*(DATA))bPXGS_U_MID_PLOT_04 0x04cPXGS_U_MID_PLOT_04_DATA_TYPE int16_tdPXGS_U_MID_PLOT_04_DATA_ENLARGE 10ePXGS_U_MID_PLOT_04_DATA_PACK(DATA) (PXGS_U_MID_PLOT_04_DATA_ENLARGE*(DATA))nPXGS_U_MID_PLOT_05 0x05oPXGS_U_MID_PLOT_05_DATA_TYPE int16_tpPXGS_U_MID_PLOT_05_DATA_ENLARGE 10qPXGS_U_MID_PLOT_05_DATA_PACK(DATA) (PXGS_U_MID_PLOT_05_DATA_ENLARGE*(DATA))zPXGS_U_MID_PLOT_06 0x06{PXGS_U_MID_PLOT_06_DATA_TYPE int16_t|PXGS_U_MID_PLOT_06_DATA_ENLARGE 1}PXGS_U_MID_PLOT_06_DATA_PACK(DATA) (DATA)†PXGS_U_MID_PLOT_07 0x07‡PXGS_U_MID_PLOT_07_DATA_TYPE int16_tˆPXGS_U_MID_PLOT_07_DATA_ENLARGE 1‰PXGS_U_MID_PLOT_07_DATA_PACK(DATA) (DATA)’PXGS_U_MID_PLOT_08 0x08“PXGS_U_MID_PLOT_08_DATA_TYPE int16_t”PXGS_U_MID_PLOT_08_DATA_ENLARGE 1•PXGS_U_MID_PLOT_08_DATA_PACK(DATA) (DATA)žPXGS_U_MID_PLOT_09 0x09ŸPXGS_U_MID_PLOT_09_DATA_TYPE int16_t PXGS_U_MID_PLOT_09_DATA_ENLARGE 100¡PXGS_U_MID_PLOT_09_DATA_PACK(DATA) (PXGS_U_MID_PLOT_09_DATA_ENLARGE*(DATA))ªPXGS_U_MID_PLOT_0A 0x0A«PXGS_U_MID_PLOT_0A_DATA_TYPE int16_t¬PXGS_U_MID_PLOT_0A_DATA_ENLARGE 100­PXGS_U_MID_PLOT_0A_DATA_PACK(DATA) (PXGS_U_MID_PLOT_0A_DATA_ENLARGE*(DATA))PXGS_U_MID_PLOT_0B 0x0B·PXGS_U_MID_PLOT_0B_DATA_TYPE int16_t¸PXGS_U_MID_PLOT_0B_DATA_ENLARGE 100¹PXGS_U_MID_PLOT_0B_DATA_PACK(DATA) (PXGS_U_MID_PLOT_0B_DATA_ENLARGE*(DATA))ÂPXGS_U_MID_PLOT_0C 0x0CÃPXGS_U_MID_PLOT_0C_DATA_TYPE int16_tÄPXGS_U_MID_PLOT_0C_DATA_ENLARGE 1ÅPXGS_U_MID_PLOT_0C_DATA_PACK(DATA) (DATA)ÎPXGS_U_MID_PLOT_0D 0x0DÏPXGS_U_MID_PLOT_0D_DATA_TYPE int16_tÐPXGS_U_MID_PLOT_0D_DATA_ENLARGE 1ÑPXGS_U_MID_PLOT_0D_DATA_PACK(DATA) (DATA)ÚPXGS_U_MID_PLOT_0E 0x0EÛPXGS_U_MID_PLOT_0E_DATA_TYPE int16_tÜPXGS_U_MID_PLOT_0E_DATA_ENLARGE 1ÝPXGS_U_MID_PLOT_0E_DATA_PACK(DATA) (DATA)æPXGS_U_MID_PLOT_0F 0x0FçPXGS_U_MID_PLOT_0F_DATA_TYPE int16_tèPXGS_U_MID_PLOT_0F_DATA_ENLARGE 1éPXGS_U_MID_PLOT_0F_DATA_PACK(DATA) (DATA)òPXGS_U_MID_PLOT_10 0x10óPXGS_U_MID_PLOT_10_DATA_TYPE int16_tôPXGS_U_MID_PLOT_10_DATA_ENLARGE 1õPXGS_U_MID_PLOT_10_DATA_PACK(DATA) (DATA)þPXGS_U_MID_PLOT_11 0x11ÿPXGS_U_MID_PLOT_11_DATA_TYPE float€PXGS_U_MID_PLOT_11_DATA_ENLARGE 1�PXGS_U_MID_PLOT_11_DATA_PACK(DATA) (DATA)ŠPXGS_U_MID_PLOT_12 0x12‹PXGS_U_MID_PLOT_12_DATA_TYPE floatŒPXGS_U_MID_PLOT_12_DATA_ENLARGE 1�PXGS_U_MID_PLOT_12_DATA_PACK(DATA) (DATA)–PXGS_U_MID_PLOT_13 0x13—PXGS_U_MID_PLOT_13_DATA_TYPE int16_t˜PXGS_U_MID_PLOT_13_DATA_ENLARGE 1™PXGS_U_MID_PLOT_13_DATA_PACK(DATA) (DATA)¢PXGS_U_MID_PLOT_14 0x14£PXGS_U_MID_PLOT_14_DATA_TYPE int16_t¤PXGS_U_MID_PLOT_14_DATA_ENLARGE 1¥PXGS_U_MID_PLOT_14_DATA_PACK(DATA) (DATA)®PXGS_U_MID_PLOT_15 0x15¯PXGS_U_MID_PLOT_15_DATA_TYPE int16_t°PXGS_U_MID_PLOT_15_DATA_ENLARGE 1±PXGS_U_MID_PLOT_15_DATA_PACK(DATA) (DATA)ºPXGS_U_MID_PLOT_16 0x16»PXGS_U_MID_PLOT_16_DATA_TYPE int16_t¼PXGS_U_MID_PLOT_16_DATA_ENLARGE 1½PXGS_U_MID_PLOT_16_DATA_PACK(DATA) (DATA)ÆPXGS_U_MID_PLOT_17 0x17ÇPXGS_U_MID_PLOT_17_DATA_TYPE int16_tÈPXGS_U_MID_PLOT_17_DATA_ENLARGE 1ÉPXGS_U_MID_PLOT_17_DATA_PACK(DATA) (DATA)ÒPXGS_U_MID_PLOT_18 0x18Ó
..\debug\pack.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] D:\WORK\Guitar\ChipTest\PAN159\PAN159-Template\SampleCode\Template\Keil789__string_h __ARMCLIB_VERSION 5060037_ARMABI __declspec(__nothrow)__STRING_DECLS __CLIBNS$__CLIBNS 7NULL8NULL 0PD
C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h¨C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] unsigned intPsize_tŠ,;<=$__CMSIS_ARMCC_H ¹__NOP __nopÀ__WFI __wfiÈ__WFE __wfeÏ__SEV __sevØ__ISB() do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0U)ã__DSB() do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U)î__DMB() do { __schedule_barrier(); __dmb(0xF); __schedule_barrier(); } while (0U)ú__REV __rev¡__ROR __ror«__BKPT(value) __breakpoint(value)Ï__CLZ __clzPD
..\..\..\Library\CMSIS\Include\cmsis_armcc.hØ
..\..\..\Library\CMSIS\Include\cmsis_armcc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] D:\WORK\Guitar\ChipTest\PAN159\PAN159-Template\SampleCode\Template\Keil;’9__get_CONTROLYa__resultYY__regControlYP<ËE__set_CONTROL$YcontrolY__regControlYP;…Q__get_IPSRYa__resultYY__regIPSRYP;¿]__get_APSRYa__resultYY__regAPSRYP;ùi__get_xPSRYa__resultYY__regXPSRYP;Áu__get_PSPYa__resultYY__regProcessStackPointerYP<Š�__set_PSP$YtopOfProcStackY__regProcessStackPointerYP;Ð�__get_MSPYa__resultYY__regMainStackPointerYP<–™__set_MSP$YtopOfMainStackY__regMainStackPointerYP;×¥__get_PRIMASKYa__resultYY__regPriMaskYP<‘±__set_PRIMASK$YpriMaskY__regPriMaskYP;×·9__RBITY$Yvaluea__resultY\resultY\s?@A*__CORE_CMINSTR_H 5`V
..\..\..\Library\CMSIS\Include\core_cmInstr.hcmsis_armcc.hÔ
..\..\..\Library\CMSIS\Include\core_cmInstr.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] D:\WORK\Guitar\ChipTest\PAN159\PAN159-Template\SampleCode\Template\KeilCDE*__CORE_CMFUNC_H 5`U
..\..\..\Library\CMSIS\Include\core_cmFunc.hcmsis_armcc.hÐ
..\..\..\Library\CMSIS\Include\core_cmFunc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] D:\WORK\Guitar\ChipTest\PAN159\PAN159-Template\SampleCode\Template\KeilGHI*__CORE_CM0_H_GENERIC ,J__CM0_CMSIS_VERSION_MAIN (0x04U)K__CM0_CMSIS_VERSION_SUB (0x1EU)L__CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | __CM0_CMSIS_VERSION_SUB )O__CORTEX_M (0x00U)S__ASM __asmT__INLINE __inlineU__STATIC_INLINE static __inline|__FPU_USED 0U£¤¯__CORE_CM0_H_DEPENDANT Ò__I volatile constÔ__O volatileÕ__IO volatileØ__IM volatile constÙ__OM volatileÚ__IOM volatile…APSR_N_Pos 31U†APSR_N_Msk (1UL << APSR_N_Pos)ˆAPSR_Z_Pos 30U‰APSR_Z_Msk (1UL << APSR_Z_Pos)‹APSR_C_Pos 29UŒAPSR_C_Msk (1UL << APSR_C_Pos)ŽAPSR_V_Pos 28U�APSR_V_Msk (1UL << APSR_V_Pos) IPSR_ISR_Pos 0U¡IPSR_ISR_Msk (0x1FFUL )¸xPSR_N_Pos 31U¹xPSR_N_Msk (1UL << xPSR_N_Pos)»xPSR_Z_Pos 30U¼xPSR_Z_Msk (1UL << xPSR_Z_Pos)¾xPSR_C_Pos 29U¿xPSR_C_Msk (1UL << xPSR_C_Pos)ÁxPSR_V_Pos 28UÂxPSR_V_Msk (1UL << xPSR_V_Pos)ÄxPSR_T_Pos 24UÅxPSR_T_Msk (1UL << xPSR_T_Pos)ÇxPSR_ISR_Pos 0UÈxPSR_ISR_Msk (0x1FFUL )ÚCONTROL_SPSEL_Pos 1UÛCONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)“SCB_CPUID_IMPLEMENTER_Pos 24U”SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)–SCB_CPUID_VARIANT_Pos 20U—SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)™SCB_CPUID_ARCHITECTURE_Pos 16UšSCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)œSCB_CPUID_PARTNO_Pos 4U�SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)ŸSCB_CPUID_REVISION_Pos 0U SCB_CPUID_REVISION_Msk (0xFUL )£SCB_ICSR_NMIPENDSET_Pos 31U¤SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)¦SCB_ICSR_PENDSVSET_Pos 28U§SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)©SCB_ICSR_PENDSVCLR_Pos 27UªSCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)¬SCB_ICSR_PENDSTSET_Pos 26U­SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)¯SCB_ICSR_PENDSTCLR_Pos 25U°SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)²SCB_ICSR_ISRPREEMPT_Pos 23U³SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)µSCB_ICSR_ISRPENDING_Pos 22USCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)¸SCB_ICSR_VECTPENDING_Pos 12U¹SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)»SCB_ICSR_VECTACTIVE_Pos 0U¼SCB_ICSR_VECTACTIVE_Msk (0x1FFUL )¿SCB_AIRCR_VECTKEY_Pos 16UÀSCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)ÂSCB_AIRCR_VECTKEYSTAT_Pos 16UÃSCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)ÅSCB_AIRCR_ENDIANESS_Pos 15UÆSCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)ÈSCB_AIRCR_SYSRESETREQ_Pos 2UÉSCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)ËSCB_AIRCR_VECTCLRACTIVE_Pos 1UÌSCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)ÏSCB_SCR_SEVONPEND_Pos 4UÐSCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)ÒSCB_SCR_SLEEPDEEP_Pos 2UÓSCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)ÕSCB_SCR_SLEEPONEXIT_Pos 1UÖSCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)ÙSCB_CCR_STKALIGN_Pos 9UÚSCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)ÜSCB_CCR_UNALIGN_TRP_Pos 3UÝSCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)àSCB_SHCSR_SVCALLPENDED_Pos 15UáSCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)ùSysTick_CTRL_COUNTFLAG_Pos 16UúSysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)üSysTick_CTRL_CLKSOURCE_Pos 2UýSysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)ÿSysTick_CTRL_TICKINT_Pos 1U€SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)‚SysTick_CTRL_ENABLE_Pos 0UƒSysTick_CTRL_ENABLE_Msk (1UL )†SysTick_LOAD_RELOAD_Pos 0U‡SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )ŠSysTick_VAL_CURRENT_Pos 0U‹SysTick_VAL_CURRENT_Msk (0xFFFFFFUL )ŽSysTick_CALIB_NOREF_Pos 31U�SysTick_CALIB_NOREF_Msk (1UL << SysT
..\..\..\Library\CMSIS\Include\core_cm0.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] D:\WORK\Guitar\ChipTest\PAN159\PAN159-Template\SampleCode\Template\Keil*£!_reserved0Y#!VY#!CY#!ZY#!NY#S¶bÏwYPAPSR_Type#‚*ô!ISRY# !_reserved0Y#S‡bHwYPIPSR_Typet�*¢!ISRY# !_reserved0Y#!TY#!_reserved1Y#!VY#!CY#!ZY#!NY#Sµb™wYPxPSR_Type"µ*Œ!_reserved0Y#!SPSELY#!_reserved1Y#SŸbGwYPCONTROL_TypeŒ×*´ Â´ISER¹#ÙYRESERVED0Î#ó´ICERê#€‹YRSERVED1#„¥´ISPR#€½YRESERVED22#„Ø´ICPRO#€ðYRESERVED3e#„�Y?RESERVED4‚#€¨´IPŸ#€tYPNVIC_Type´ö*Ô(CPUIDZ#ICSR´#RESERVED0Y#AIRCR´# SCR´#CCR´#RESERVED1Y#»´SHP2#SHCSR´#$YtTPSCB_TypeÌ�*¤ CTRL´#LOAD´#VAL´#CALIBZ# PSysTick_Typeoö<Ü õNVIC_EnableIRQ$!IRQn<€
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˜NVIC_SetPendingIRQ$!IRQn<Œ £NVIC_ClearPendingIRQ$!IRQn<À °NVIC_SetPriority$!IRQn$Ypriority;ú ÈNVIC_GetPriorityY$!IRQna__resultY<” ÚNVIC_SystemReset;Í �SysTick_ConfigY$Yticksa__resultYKLMN__SYSTEM_MINI58SERIES_H__ __XTAL12M (12000000UL)__XTAL32K (32768UL)__IRC10K (10000UL)__XTAL __XTAL12M__HXT __XTAL __HIRC (22118400UL)lb
..\..\..\Library\Device\Nuvoton\Mini58Series\Include\system_Mini58Series.h<
..\..\..\Library\Device\Nuvoton\Mini58Series\Include\system_Mini58Series.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] D:\WORK\Guitar\ChipTest\PAN159\PAN159-Template\SampleCode\Template\Keilq__HSIYqSystemCoreClockYqCyclesPerUsYqPllClockYI@ð__HSIþSystemCoreClockCyclesPerUs*PllClockPQR __SYS_H__ !ADC_RST ((0x4<<24) | SYS_IPRST1_ADCRST_Pos )"ACMP_RST ((0x4<<24) | SYS_IPRST1_ACMPRST_Pos )#PWM0_RST ((0x4<<24) | SYS_IPRST1_PWM0RST_Pos )$UART0_RST ((0x4<<24) | SYS_IPRST1_UART0RST_Pos )%UART1_RST ((0x4<<24) | SYS_IPRST1_UART1RST_Pos )&SPI0_RST ((0x4<<24) | SYS_IPRST1_SPI0RST_Pos )'I2C0_RST ((0x4<<24) | SYS_IPRST1_I2C0RST_Pos )(I2C1_RST ((0x4<<24) | SYS_IPRST1_I2C1RST_Pos ))TMR1_RST ((0x4<<24) | SYS_IPRST1_TMR1RST_Pos )*TMR0_RST ((0x4<<24) | SYS_IPRST1_TMR0RST_Pos )+GPIO_RST ((0x4<<24) | SYS_IPRST1_GPIORST_Pos )1SYS_BODCTL_BOD_RST_EN (1UL<<SYS_BODCTL_BODRSTEN_Pos)2SYS_BODCTL_BOD_INTERRUPT_EN (0UL<<SYS_BODCTL_BODRSTEN_Pos)3SYS_BODCTL_BODVL_4_4V (3UL<<SYS_BODCTL_BODVL_Pos)4SYS_BODCTL_BODVL_3_7V (2UL<<SYS_BODCTL_BODVL_Pos)5SYS_BODCTL_BODVL_2_7V (1UL<<SYS_BODCTL_BODVL_Pos)6SYS_BODCTL_BODVL_2_2V (0UL<<SYS_BODCTL_BODVL_Pos)<SYS_MFP_TYPE_Msk(bit) (1UL << ((bit) +16))=SYS_MFP_ALT_Msk(bit) (1UL << ((bit) + 8))>SYS_MFP_MFP_Msk(bit) (1UL << ((bit) ))@SYS_MFP_P00_GPIO 0x00000000ULASYS_MFP_P00_UART0_nCTS 0x00000100ULBSYS_MFP_P00_UART0_TXD 0x00000101ULCSYS_MFP_P00_Msk 0x00000101ULESYS_MFP_P01_GPIO 0x00000000ULFSYS_MFP_P01_SPI0_SS 0x00000002ULGSYS_MFP_P01_UART0_nRTS 0x00000200ULHSYS_MFP_P01_UART0_RXD 0x00000202ULISYS_MFP_P01_Msk 0x00000202ULKSYS_MFP_P04_GPIO 0x00000000ULLSYS_MFP_P04_PWM0_CH5 0x00001010ULMSYS_MFP_P04_SPI0_SS 0x00001000ULNSYS_MFP_P04_Msk 0x00001010ULPSYS_MFP_P05_GPIO 0x00000000ULQSYS_MFP_P05_PWM0_CH4 0x00002020ULRSYS_MFP_P05_SPI0_MOSI 0x00002000ULSSYS_MFP_P05_Msk 0x00002020ULUSYS_MFP_P06_GPIO 0x00000000ULVSYS_MFP_P06_PWM0_CH1 0x00004040ULWSYS_MFP_P06_SPI0_MISO 0x00004000ULXSYS_MFP_P06_Msk 0x00004040ULZSYS_MFP_P07_GPIO 0x00000000UL[SYS_MFP_P07_PWM0_CH0 0x00008080UL\SYS_MFP_P07_SPI0_CLK 0x00008000UL]SYS_MFP_P07_Msk 0x00008080UL_SYS_MFP_P10_ACMP0_P1 0x00000101UL`SYS_MFP_P10_ADC_CH1 0x00000001ULaSYS_MFP_P10_GPIO 0x00000000ULbSYS_MFP_P10_Msk 0x00000101ULdSYS_MFP_P12_ACMP0_P2 0x00000404ULeSYS_MFP_P12_ADC_CH2 0x00000004ULfSYS_MFP_P12_GPIO 0x00000000ULgSYS_MFP_P12_UART0_RXD 0x00000400ULhSYS_MFP_P12_PWM0_CH0 0x04000000ULiSYS_MFP_P12_Msk 0x04000404ULkSYS_MFP_P13_ACMP0_P3 0x00000808ULlSYS_MFP_P13_ADC_CH3 0x00000008ULmSYS_MFP_P13_GPIO 0x00000000ULnSYS_MFP_P13_UART0_TXD 0x00000800ULoSYS_MFP_P13_PWM0_CH1 0x08000000ULpSYS_MFP_P13_Msk 0x08000808ULrSYS_MFP_P14_ACMP0_N 0x00001010ULsSYS_MFP_P14_ADC_CH4 0x00000010ULtSYS_MFP_P14_GPIO 0x00000000ULuSYS_MFP_P14_UART1_RXD 0x00001000ULvSYS_MFP_P14_PWM0_CH4 0x10000000ULwSYS_MFP_P14_Msk 0x10001010ULySYS_MFP_P15_ACMP0_P0 0x00002020ULzSYS_MFP_P15_ADC_CH5 0x00000020UL{SYS_MFP_P15_GPIO 0x00000000UL|SYS_MFP_P15_UART1_TXD 0x00002000UL}SYS_MFP_P15_Msk 0x00002020ULSYS_MFP_P22_GPIO 0x00000000UL€SYS_MFP_P22_I2C1_SCL 0x00000404UL�SYS_MFP_P22_PWM0_CH0 0x00000400UL‚SYS_MFP_P22_Msk 0x00000404UL„SYS_MFP_P23_GPIO 0x00000000UL…SYS_MFP_P23_I2C1_SDA 0x00000808UL†SYS_MFP_P23_PWM0_CH1 0x00000800UL‡SYS_MFP_P23_Msk 0x00000808UL‰SYS_MFP_P24_GPIO 0x00000000ULŠSYS_MFP_P24_PWM0_CH2 0x00001000UL‹SYS_MFP_P24_UART1_RXD 0x00000010ULŒSYS_MFP_P24_Msk 0x00001010ULŽSYS_MFP_P25_GPIO 0x00000000UL�SYS_MFP_P25_PWM0_CH3 0x00002000UL�SYS_MFP_P25_UART1_TXD 0x00000020UL‘SYS_MFP_P25_Msk 0x00002020UL“SYS_MFP_P26_ACMP1_O 0x00004040UL”SYS_MFP_P26_GPIO 0x00000000UL•SYS_MFP_P26_PWM0_CH4 0x00004000UL–SYS_MFP_P26_Msk 0x00004040UL˜SYS_MFP_P30_ACMP1_N 0x00000100UL™SYS_MFP_P30_ADC_CH6 0x00000101ULšSYS_MFP_P30_GPIO 0x00000000UL›SYS_MFP_P30_Msk 0x00000101UL�SYS_MFP_P31_ACMP1_P0 0x00000200ULžSYS_MFP_P31_ADC_CH7 0x00000202U
..\..\..\Library\StdDriver\inc\sys.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] D:\WORK\Guitar\ChipTest\PAN159\PAN159-Template\SampleCode\Template\Keil<á¢SYS_UnlockReg<ö´SYS_LockRegTUV __CLK_H__ "FREQ_25MHZ 25000000#FREQ_50MHZ 50000000$FREQ_72MHZ 72000000%FREQ_100MHZ 100000000&FREQ_200MHZ 200000000'FREQ_250MHZ 250000000(FREQ_500MHZ 500000000.CLK_PWRCTL_XTL12M 0x01UL/CLK_PWRCTL_XTLEN_HXT 0x01UL0CLK_PWRCTL_XTL32K 0x02UL1CLK_PWRCTL_XTLEN_LXT 0x02UL6CLK_CLKSEL0_HCLKSEL_XTAL 0x00UL7CLK_CLKSEL0_HCLKSEL_HXT 0x00UL8CLK_CLKSEL0_HCLKSEL_LXT 0x00UL9CLK_CLKSEL0_HCLKSEL_PLL 0x02UL:CLK_CLKSEL0_HCLKSEL_LIRC 0x03UL;CLK_CLKSEL0_HCLKSEL_HIRC 0x07UL<CLK_CLKSEL0_STCLKSEL_XTAL 0x00UL=CLK_CLKSEL0_STCLKSEL_XTAL_DIV2 0x10UL>CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 0x18UL?CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 0x38UL@CLK_CLKSEL0_STCLKSEL_HCLK 0x08ULECLK_CLKSEL1_WDTSEL_XTAL 0x00000000ULFCLK_CLKSEL1_WDTSEL_HCLK_DIV2048 0x00000002ULGCLK_CLKSEL1_WDTSEL_IRC10K 0x00000003ULHCLK_CLKSEL1_WDTSEL_LIRC 0x00000003ULICLK_CLKSEL1_ADCSEL_XTAL 0x00000000ULJCLK_CLKSEL1_ADCSEL_PLL 0x00000004ULKCLK_CLKSEL1_ADCSEL_HCLK 0x00000008ULLCLK_CLKSEL1_ADCSEL_HIRC 0x0000000CULMCLK_CLKSEL1_SPISEL_XTAL 0x00000000ULNCLK_CLKSEL1_SPISEL_HCLK 0x00000010ULOCLK_CLKSEL1_SPISEL_PLL 0x00000020ULPCLK_CLKSEL1_TMR0SEL_XTAL 0x00000000ULQCLK_CLKSEL1_TMR0SEL_LIRC 0x00000100ULRCLK_CLKSEL1_TMR0SEL_HCLK 0x00000200ULSCLK_CLKSEL1_TMR0SEL_TM0 0x00000300ULTCLK_CLKSEL1_TMR0SEL_HIRC 0x00000700ULUCLK_CLKSEL1_TMR1SEL_XTAL 0x00000000ULVCLK_CLKSEL1_TMR1SEL_LIRC 0x00001000ULWCLK_CLKSEL1_TMR1SEL_HCLK 0x00002000ULXCLK_CLKSEL1_TMR1SEL_TM1 0x00003000ULYCLK_CLKSEL1_TMR1SEL_HIRC 0x00007000ULZCLK_CLKSEL1_UARTSEL_XTAL 0x00000000UL[CLK_CLKSEL1_UARTSEL_PLL 0x01000000UL\CLK_CLKSEL1_UARTSEL_HIRC 0x02000000UL]CLK_CLKSEL1_PWMCH01SEL_HCLK 0x20000000UL^CLK_CLKSEL1_PWMCH23SEL_HCLK 0x80000000ULdCLK_CLKSEL2_CLKOSEL_XTAL 0x00000000ULeCLK_CLKSEL2_CLKOSEL_HXT 0x00000000ULfCLK_CLKSEL2_CLKOSEL_LXT 0x00000000ULgCLK_CLKSEL2_CLKOSEL_LIRC 0x00000004ULhCLK_CLKSEL2_CLKOSEL_HCLK 0x00000008ULiCLK_CLKSEL2_CLKOSEL_HIRC 0x0000000CULjCLK_CLKSEL2_PWMCH45SEL_HCLK 0x00000020ULkCLK_CLKSEL2_WWDTSEL_HCLK_DIV2048 0x00020000ULlCLK_CLKSEL2_WWDTSEL_LIRC 0x00030000ULrCLK_CLKDIV_ADC(x) (((x)-1) << 16)sCLK_CLKDIV_UART(x) (((x)-1) << 8)tCLK_CLKDIV_HCLK(x) ((x)-1)yCLK_PLLCTL_PLLSRC_HXT 0x00000000ULzCLK_PLLCTL_PLLSRC_HIRC 0x00080000UL|CLK_PLLCTL_NF(x) ((x)-2)}CLK_PLLCTL_NR(x) (((x)-2)<<9)CLK_PLLCTL_NO_1 0x0000UL€CLK_PLLCTL_NO_2 0x4000UL�CLK_PLLCTL_NO_4 0xC000ULƒCLK_PLLCTL_72MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 24) | CLK_PLLCTL_NO_2)„CLK_PLLCTL_96MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 32) | CLK_PLLCTL_NO_2)…CLK_PLLCTL_100MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF( 50) | CLK_PLLCTL_NO_2)‡CLK_PLLCTL_72MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 26) | CLK_PLLCTL_NO_2)ˆCLK_PLLCTL_96MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(13)| CLK_PLLCTL_NF(113) | CLK_PLLCTL_NO_2)‰CLK_PLLCTL_100MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 36) | CLK_PLLCTL_NO_2)ŽMODULE_APBCLK(x) ((x >>31) & 0x1)�MODULE_CLKSEL(x) ((x >>29) & 0x3)�MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf)‘MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f)’MODULE_CLKDIV(x) ((x >>18) & 0x3)“MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff)”MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f)•MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f)–MODULE_NoMsk 0x0—NA MODULE_NoMsk™MODULE_APBCLK_ENC(x) (((x) & 0x01) << 31)šMODULE_CLKSEL_ENC(x) (((x) & 0x03) << 29)›MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0f) << 25)œMODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20)�MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18)žMODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10)ŸMODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5) MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0)¤ISP_MODULE (( 0UL<<31)|( 0<<29)|( MODULE_NoMsk<<25)
..\..\..\Library\StdDriver\inc\clk.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] D:\WORK\Guitar\ChipTest\PAN159\PAN159-Template\SampleCode\Template\Keil;æÄCLK_GetPLLClockFreqYa__resultY\u32PllFreqY\u32PllRegY\u32FINY\u32NFY\u32NRY\u32NOYØ:\au8NoTblMXYZ __ACMP_H__ !ACMP_VNEG_PIN (0xFFUL)"ACMP_VNEG_BANDGAP (0x00UL)#ACMP_VNEG_4_OVER_24_VDD (0x80UL)$ACMP_VNEG_5_OVER_24_VDD (0x81UL)%ACMP_VNEG_6_OVER_24_VDD (0x82UL)&ACMP_VNEG_7_OVER_24_VDD (0x83UL)'ACMP_VNEG_8_OVER_24_VDD (0x84UL)(ACMP_VNEG_9_OVER_24_VDD (0x85UL))ACMP_VNEG_10_OVER_24_VDD (0x86UL)*ACMP_VNEG_11_OVER_24_VDD (0x87UL)+ACMP_VNEG_12_OVER_24_VDD (0x88UL),ACMP_VNEG_13_OVER_24_VDD (0x89UL)-ACMP_VNEG_14_OVER_24_VDD (0x8AUL).ACMP_VNEG_15_OVER_24_VDD (0x8BUL)/ACMP_VNEG_16_OVER_24_VDD (0x8CUL)0ACMP_VNEG_17_OVER_24_VDD (0x8DUL)1ACMP_VNEG_18_OVER_24_VDD (0x8EUL)2ACMP_VNEG_19_OVER_24_VDD (0x8FUL)3ACMP_HYSTERESIS_ENABLE (1UL << ACMP_CTL_HYSSEL_Pos)4ACMP_HYSTERESIS_DISABLE (0UL)5ACMP_CH0_POSPIN_P15 (0UL)6ACMP_CH0_POSPIN_P10 (1UL << ACMP_CTL_POSSEL_Pos)7ACMP_CH0_POSPIN_P12 (2UL << ACMP_CTL_POSSEL_Pos)8ACMP_CH0_POSPIN_P13 (3UL << ACMP_CTL_POSSEL_Pos)9ACMP_CH1_POSPIN_P31 (0UL):ACMP_CH1_POSPIN_P32 (1UL << ACMP_CTL_POSSEL_Pos);ACMP_CH1_POSPIN_P34 (2UL << ACMP_CTL_POSSEL_Pos)<ACMP_CH1_POSPIN_P35 (3UL << ACMP_CTL_POSSEL_Pos)=ACMP_FILTSEL_OFF (0UL)>ACMP_FILTSEL_1PCLK (1UL << ACMP_CTL_FILTSEL_Pos)?ACMP_FILTSEL_2PCLK (2UL << ACMP_CTL_FILTSEL_Pos)@ACMP_FILTSEL_4PCLK (3UL << ACMP_CTL_FILTSEL_Pos)AACMP_FILTSEL_8PCLK (4UL << ACMP_CTL_FILTSEL_Pos)BACMP_FILTSEL_16PCLK (5UL << ACMP_CTL_FILTSEL_Pos)CACMP_FILTSEL_32PCLK (6UL << ACMP_CTL_FILTSEL_Pos)DACMP_FILTSEL_64PCLK (7UL << ACMP_CTL_FILTSEL_Pos)EACMP_FILTSEL_128PCLK (8UL << ACMP_CTL_FILTSEL_Pos)FACMP_FILTSEL_256PCLK (9UL << ACMP_CTL_FILTSEL_Pos)GACMP_FILTSEL_512PCLK (10UL << ACMP_CTL_FILTSEL_Pos)lACMP_SET_NEG_SRC(acmp,u32ChNum,u32Src) do{ if(u32Src == ACMP_VNEG_PIN) ACMP->CTL[u32ChNum] &= ~ACMP_CTL_NEGSEL_Msk; else { ACMP->CTL[u32ChNum] |= ACMP_CTL_NEGSEL_Msk; ACMP->VREF = u32Src; } }while(0)|ACMP_ENABLE_HYSTERESIS(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_HYSSEL_Msk)…ACMP_DISABLE_HYSTERESIS(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_HYSSEL_Msk)ŽACMP_ENABLE_INT(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_ACMPIE_Msk)—ACMP_DISABLE_INT(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_ACMPIE_Msk)¡ACMP_ENABLE(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_ACMPEN_Msk)ªACMP_DISABLE(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_ACMPEN_Msk)³ACMP_GET_OUTPUT(acmp,u32ChNum) (ACMP->STATUS & (ACMP_STATUS_ACMPO0_Msk<<(u32ChNum))?1:0)¼ACMP_GET_INT_FLAG(acmp,u32ChNum) (ACMP->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<(u32ChNum))?1:0)ÅACMP_CLR_INT_FLAG(acmp,u32ChNum) (ACMP->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<(u32ChNum)))ÓACMP_SELECT_P(acmp,u32ChNum,u32Pin) (ACMP->CTL[u32ChNum] = (ACMP->CTL[u32ChNum] & ~ACMP_CTL_POSSEL_Msk) | (u32Pin))ëACMP_CRV_SEL(acmp,u32Level) (ACMP->VREF = (ACMP->VREF & ~ACMP_VREF_CRVCTL_Msk) | ((u32Level) & ~ACMP_VREF_IREFSEL_Msk))òACMP_ENABLE_CRV(acmp) (ACMP->VREF |= ACMP_VREF_IREFSEL_Msk)ùACMP_DISABLE_CRV(acmp) (ACMP->VREF &= ~ACMP_VREF_IREFSEL_Msk)‚ACMP_ENABLE_FALLING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_FTRGEN_Msk)‹ACMP_DISABLE_FALLING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_FTRGEN_Msk)”ACMP_ENABLE_RISING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_RTRGEN_Msk)�ACMP_DISABLE_RISING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_RTRGEN_Msk)²ACMP_SET_FILTER(acmp,u32ChNum,u32Cnt) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[u32ChNum] & ~ACMP_CTL_FILTSEL_Msk) | (u32Cnt))H=
..\..\..\Library\StdDriver\inc\acmp.hÌ
..\..\..\Library\StdDriver\inc\acmp.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] D:\WORK\Guitar\ChipTest\PAN159\PAN159-Template\SampleCode\Template\Keil\]^ __ADC_H__  ADC_CH7_EXT (0UL)!ADC_CH7_BGP (ADC_CHEN_CH7SEL_Msk)"ADC_CMP0_LESS_THAN (0UL << ADC_CMP0_CMPCOND_Pos)#ADC_CMP1_LESS_THAN (0UL << ADC_CMP1_CMPCOND_Pos)$ADC_CMP0_GREATER_OR_EQUAL_TO (1ul << ADC_CMP0_CMPCOND_Pos)%ADC_CMP1_GREATER_OR_EQUAL_TO (1ul << ADC_CMP1_CMPCOND_Pos)&ADC_TRIGGER_BY_EXT_PIN (0UL)'ADC_TRIGGER_BY_PWM (ADC_CTL_HWTRGSEL_Msk)(ADC_FALLING_EDGE_TRIGGER (0UL))ADC_RISING_EDGE_TRIGGER (ADC_CTL_HWTRGCOND_Msk)*ADC_ADIF_INT (ADC_STATUS_ADIF_Msk)+ADC_CMP0_INT (ADC_STATUS_ADCMPF0_Msk),ADC_CMP1_INT (ADC_STATUS_ADCMPF1_Msk)-ADC_SAMPLE_CLOCK_0 (0UL).ADC_SAMPLE_CLOCK_1 (1UL)/ADC_SAMPLE_CLOCK_2 (2UL)0ADC_SAMPLE_CLOCK_4 (3UL)1ADC_SAMPLE_CLOCK_8 (4UL)2ADC_SAMPLE_CLOCK_16 (5UL)3ADC_SAMPLE_CLOCK_32 (6UL)4ADC_SAMPLE_CLOCK_64 (7UL)5ADC_SAMPLE_CLOCK_128 (8UL)6ADC_SAMPLE_CLOCK_256 (9UL)7ADC_SAMPLE_CLOCK_512 (10UL)8ADC_SAMPLE_CLOCK_1024 (11UL)9ADC_SEQMODE_TYPE_23SHUNT (0UL):ADC_SEQMODE_TYPE_1SHUNT (1UL);ADC_SEQMODE_MODESELECT_CH01 (0UL)<ADC_SEQMODE_MODESELECT_CH12 (1UL)=ADC_SEQMODE_MODESELECT_CH02 (2UL)>ADC_SEQMODE_PWM0_RISING (0UL)?ADC_SEQMODE_PWM0_CENTER (1UL)@ADC_SEQMODE_PWM0_FALLING (2UL)AADC_SEQMODE_PWM0_PERIOD (3UL)BADC_SEQMODE_PWM2_RISING (4UL)CADC_SEQMODE_PWM2_CENTER (5UL)DADC_SEQMODE_PWM2_FALLING (6UL)EADC_SEQMODE_PWM2_PERIOD (7UL)FADC_SEQMODE_PWM4_RISING (8UL)GADC_SEQMODE_PWM4_CENTER (9UL)HADC_SEQMODE_PWM4_FALLING (10UL)IADC_SEQMODE_PWM4_PERIOD (11UL)\ADC_CONFIG_CH7(adc,u32Source) (ADC->CHEN = ((adc)->CHEN & ~ADC_CHEN_CH7SEL_Msk) | (u32Source))eADC_GET_CONVERSION_DATA(adc,u32ChNum) ((adc)->DAT & ADC_DAT_RESULT_Msk)qADC_GET_INT_FLAG(adc,u32Mask) ((adc)->STATUS & (u32Mask))}ADC_CLR_INT_FLAG(adc,u32Mask) ((adc)->STATUS = ((adc)->STATUS & ~(ADC_STATUS_ADIF_Msk | ADC_STATUS_ADCMPF0_Msk | ADC_STATUS_ADCMPF1_Msk)) | (u32Mask))‰ADC_IS_BUSY(adc) ((adc)->STATUS & ADC_STATUS_BUSY_Msk ? 1 : 0)”ADC_IS_DATA_OVERRUN(adc,u32ChNum) ((adc)->STATUS & ADC_STATUS_OV_Msk ? 1 : 0)ŸADC_IS_DATA_VALID(adc,u32ChNum) ((adc)->STATUS & ADC_STATUS_VALID_Msk ? 1 : 0)§ADC_POWER_DOWN(adc) ((adc)->CTL &= ~ADC_CTL_ADCEN_Msk)¯ADC_POWER_ON(adc) ((adc)->CTL |= ADC_CTL_ADCEN_Msk)ÀADC_ENABLE_CMP0(adc,u32ChNum,u32Condition,u32Data,u32MatchCount) (ADC->CMP0 = ((u32ChNum) << ADC_CMP0_CMPCH_Pos) | (u32Condition) | ((u32Data) << ADC_CMP0_CMPDAT_Pos) | (((u32MatchCount) - 1) << ADC_CMP0_CMPMCNT_Pos) | ADC_CMP0_ADCMPIE_Msk | ADC_CMP0_ADCMPEN_Msk)ÐADC_DISABLE_CMP0(adc) ((adc)->CMP0 = 0)áADC_ENABLE_CMP1(adc,u32ChNum,u32Condition,u32Data,u32MatchCount) (ADC->CMP1 = ((u32ChNum) << ADC_CMP1_CMPCH_Pos) | (u32Condition) | ((u32Data) << ADC_CMP1_CMPDAT_Pos) | ((u32MatchCount - 1) << ADC_CMP1_CMPMCNT_Pos) | ADC_CMP1_ADCMPEN_Msk)ðADC_DISABLE_CMP1(adc) ((adc)->CMP1 = 0)ûADC_SET_INPUT_CHANNEL(adc,u32Mask) ((adc)->CHEN = (ADC->CHEN & ~ADC_CHEN_CHEN0_Msk) | (u32Mask))ƒADC_START_CONV(adc) ((adc)->CTL |= ADC_CTL_SWTRG_Msk)‹ADC_STOP_CONV(adc) ((adc)->CTL &= ~ADC_CTL_SWTRG_Msk)H<
..\..\..\Library\StdDriver\inc\adc.hÈ
..\..\..\Library\StdDriver\inc\adc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] D:\WORK\Guitar\ChipTest\PAN159\PAN159-Template\SampleCode\Template\Keil`ab __FMC_H__ !FMC_APROM_BASE 0x00000000UL"FMC_APROM_END 0x00008000UL#FMC_LDROM_BASE 0x00100000UL$FMC_LDROM_END 0x00100A00UL%FMC_SPROM_BASE 0x00200000UL&FMC_SPROM_END 0x00200200UL'FMC_CONFIG_BASE 0x00300000UL)FMC_FLASH_PAGE_SIZE 0x200*FMC_LDROM_SIZE 0xA00+FMC_SPROM_SIZE 0x2001FMC_ISPCMD_READ 0x002FMC_ISPCMD_READ_UID 0x043FMC_ISPCMD_READ_CID 0x0B4FMC_ISPCMD_READ_PID 0x0C5FMC_ISPCMD_READ_CRC32 0x0D6FMC_ISPCMD_PROGRAM 0x217FMC_ISPCMD_PAGE_ERASE 0x228FMC_ISPCMD_CAL_CRC32 0x2D9FMC_ISPCMD_VECMAP 0x2EBFMC_SET_APROM_BOOT() (FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk)CFMC_SET_LDROM_BOOT() (FMC->ISPCTL |= FMC_ISPCTL_BS_Msk)DFMC_DISABLE_AP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk)EFMC_DISABLE_SP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_SPUEN_Msk)FFMC_DISABLE_CFG_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk)GFMC_DISABLE_LD_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk)HFMC_DISABLE_ISP() (FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk)IFMC_ENABLE_AP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk)JFMC_ENABLE_SP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_SPUEN_Msk)KFMC_ENABLE_LD_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk)LFMC_ENABLE_CFG_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk)MFMC_ENABLE_ISP() (FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk)NFMC_GET_FAIL_FLAG() ((FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) ? 1 : 0)H<
..\..\..\Library\StdDriver\inc\fmc.hÈ
..\..\..\Library\StdDriver\inc\fmc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] D:\WORK\Guitar\ChipTest\PAN159\PAN159-Template\SampleCode\Template\Keildef __GPIO_H__ GPIO_PIN_MAX 8$GPIO_MODE_INPUT 0x0UL%GPIO_MODE_OUTPUT 0x1UL&GPIO_MODE_OPEN_DRAIN 0x2UL'GPIO_MODE_QUASI 0x3UL,GPIO_INT_RISING 0x00010000UL-GPIO_INT_FALLING 0x00000001UL.GPIO_INT_BOTH_EDGE 0x00010001UL/GPIO_INT_HIGH 0x01010000UL0GPIO_INT_LOW 0x01000001UL5GPIO_INTTYPE_EDGE 0UL6GPIO_INTTYPE_LEVEL 1UL;GPIO_DBCTL_ICLK_ON 0x00000020UL<GPIO_DBCTL_ICLK_OFF 0x00000000UL>GPIO_DBCTL_DBCLKSRC_IRC10K 0x00000010UL?GPIO_DBCTL_DBCLKSRC_HCLK 0x00000000ULAGPIO_DBCTL_DBCLKSEL_1 0x00000000ULBGPIO_DBCTL_DBCLKSEL_2 0x00000001ULCGPIO_DBCTL_DBCLKSEL_4 0x00000002ULDGPIO_DBCTL_DBCLKSEL_8 0x00000003ULEGPIO_DBCTL_DBCLKSEL_16 0x00000004ULFGPIO_DBCTL_DBCLKSEL_32 0x00000005ULGGPIO_DBCTL_DBCLKSEL_64 0x00000006ULHGPIO_DBCTL_DBCLKSEL_128 0x00000007ULIGPIO_DBCTL_DBCLKSEL_256 0x00000008ULJGPIO_DBCTL_DBCLKSEL_512 0x00000009ULKGPIO_DBCTL_DBCLKSEL_1024 0x0000000AULLGPIO_DBCTL_DBCLKSEL_2048 0x0000000BULMGPIO_DBCTL_DBCLKSEL_4096 0x0000000CULNGPIO_DBCTL_DBCLKSEL_8192 0x0000000DULOGPIO_DBCTL_DBCLKSEL_16384 0x0000000EULPGPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL`GPIO_PIN_ADDR(port,pin) (*((volatile uint32_t *)((GPIOBIT0_BASE+(0x20*(port))) + ((pin)<<2))))aP00 GPIO_PIN_ADDR(0, 0)bP01 GPIO_PIN_ADDR(0, 1)cP02 GPIO_PIN_ADDR(0, 2)dP03 GPIO_PIN_ADDR(0, 3)eP04 GPIO_PIN_ADDR(0, 4)fP05 GPIO_PIN_ADDR(0, 5)gP06 GPIO_PIN_ADDR(0, 6)hP07 GPIO_PIN_ADDR(0, 7)iP10 GPIO_PIN_ADDR(1, 0)jP11 GPIO_PIN_ADDR(1, 1)kP12 GPIO_PIN_ADDR(1, 2)lP13 GPIO_PIN_ADDR(1, 3)mP14 GPIO_PIN_ADDR(1, 4)nP15 GPIO_PIN_ADDR(1, 5)oP16 GPIO_PIN_ADDR(1, 6)pP17 GPIO_PIN_ADDR(1, 7)qP20 GPIO_PIN_ADDR(2, 0)rP21 GPIO_PIN_ADDR(2, 1)sP22 GPIO_PIN_ADDR(2, 2)tP23 GPIO_PIN_ADDR(2, 3)uP24 GPIO_PIN_ADDR(2, 4)vP25 GPIO_PIN_ADDR(2, 5)wP26 GPIO_PIN_ADDR(2, 6)xP27 GPIO_PIN_ADDR(2, 7)yP30 GPIO_PIN_ADDR(3, 0)zP31 GPIO_PIN_ADDR(3, 1){P32 GPIO_PIN_ADDR(3, 2)|P33 GPIO_PIN_ADDR(3, 3)}P34 GPIO_PIN_ADDR(3, 4)~P35 GPIO_PIN_ADDR(3, 5)P36 GPIO_PIN_ADDR(3, 6)€P37 GPIO_PIN_ADDR(3, 7)�P40 GPIO_PIN_ADDR(4, 0)‚P41 GPIO_PIN_ADDR(4, 1)ƒP42 GPIO_PIN_ADDR(4, 2)„P43 GPIO_PIN_ADDR(4, 3)…P44 GPIO_PIN_ADDR(4, 4)†P45 GPIO_PIN_ADDR(4, 5)‡P46 GPIO_PIN_ADDR(4, 6)ˆP47 GPIO_PIN_ADDR(4, 7)‰P50 GPIO_PIN_ADDR(5, 0)ŠP51 GPIO_PIN_ADDR(5, 1)‹P52 GPIO_PIN_ADDR(5, 2)ŒP53 GPIO_PIN_ADDR(5, 3)�P54 GPIO_PIN_ADDR(5, 4)ŽP55 GPIO_PIN_ADDR(5, 5) GPIO_CLR_INT_FLAG(gpio,u32PinMask) ((gpio)->INTSRC = u32PinMask)¬GPIO_DISABLE_DEBOUNCE(gpio,u32PinMask) ((gpio)->DBEN &= ~u32PinMask)¸GPIO_ENABLE_DEBOUNCE(gpio,u32PinMask) ((gpio)->DBEN |= u32PinMask)ÄGPIO_DISABLE_DIGITAL_PATH(gpio,u32PinMask) ((gpio)->DINOFF |= (u32PinMask << 16))ÐGPIO_ENABLE_DIGITAL_PATH(gpio,u32PinMask) ((gpio)->DINOFF &= ~(u32PinMask << 16))ÜGPIO_DISABLE_DOUT_MASK(gpio,u32PinMask) ((gpio)->DATMSK &= ~u32PinMask)èGPIO_ENABLE_DOUT_MASK(gpio,u32PinMask) ((gpio)->DATMSK |= u32PinMask)õGPIO_GET_INT_FLAG(gpio,u32PinMask) ((gpio)->INTSRC & u32PinMask)‰GPIO_SET_DEBOUNCE_TIME(clksrc,clksel) (GPIO->DBCTL = (GP_DBCTL_ICLKON_Msk | clksrc | clksel))”GPIO_GET_IN_DATA(gpio) ((gpio)->PIN) GPIO_SET_OUT_DATA(gpio,data) ((gpio)->DOUT = (data))«GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1)¹GPIO_EnableEINT0 GPIO_EnableIntÆGPIO_DisableEINT0 GPIO_DisableIntÕGPIO_EnableEINT1 GPIO_EnableIntâGPIO_DisableEINT1 GPIO_DisableIntH=
..\..\..\Library\StdDriver\inc\gpio.hÌ
..\..\..\Library\StdDriver\inc\gpio.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] D:\WORK\Guitar\ChipTest\PAN159\PAN159-Template\SampleCode\Template\Keilhij __I2C_H__ !I2C_STA 0x20"I2C_STO 0x10#I2C_SI 0x08$I2C_AA 0x043I2C_SET_CONTROL_REG(i2c,u8Ctrl) ( (i2c)->CTL = ((i2c)->CTL & ~0x3c) | u8Ctrl ):I2C_START(i2c) ( (i2c)->CTL = ((i2c)->CTL & ~I2C_CTL_SI_Msk) | I2C_CTL_STA_Msk )AI2C_STOP(i2c) do { (i2c)->CTL |= (I2C_CTL_SI_Msk | I2C_CTL_STO_Msk); while((i2c)->CTL & I2C_CTL_STO_Msk); } while(0)LI2C_WAIT_READY(i2c) while(!((i2c)->CTL & I2C_CTL_SI_Msk))SI2C_DISABLE_FIFO(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_TWOLVFIFO_Msk )ZI2C_ENABLE_FIFO(i2c) ( (i2c)->CTL1 |= I2C_CTL1_TWOLVFIFO_Msk )aI2C_DISABLE_CLOCK_STRETCH(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_NSTRETCH_Msk )hI2C_ENABLE_CLOCK_STRETCH(i2c) ( (i2c)->CTL1 |= I2C_CTL1_NSTRETCH_Msk )oI2C_DISABLE_OVERRUN_INT(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_OVIEN_Msk )vI2C_ENABLE_OVERRUN_INT(i2c) ( (i2c)->CTL1 |= I2C_CTL1_OVIEN_Msk )}I2C_ENABLE_UNDERRUN_INT(i2c) ( (i2c)->CTL1 |= I2C_CTL1_URIEN_Msk )„I2C_DISABLE_UNDERRUN_INT(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_URIEN_Msk )‹I2C_GET_DATA(i2c) ( (i2c)->DAT )“I2C_SET_DATA(i2c,u8Data) ( (i2c)->DAT = u8Data )šI2C_GET_STATUS(i2c) ( (i2c)->STATUS )£I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 )¬I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->STATUS1 & I2C_STATUS1_WKIF_Msk) == I2C_STATUS1_WKIF_Msk ? 1:0 )³I2C_CLEAR_WAKEUP_FLAG(i2c) ( (i2c)->STATUS1 = I2C_STATUS1_WKIF_Msk )H<
..\..\..\Library\StdDriver\inc\i2c.hÈ
..\..\..\Library\StdDriver\inc\i2c.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] D:\WORK\Guitar\ChipTest\PAN159\PAN159-Template\SampleCode\Template\Keillmn __PWM_H__ PWM_CHANNEL_NUM (6) PWM_CLK_DIV_1 (4UL)!PWM_CLK_DIV_2 (0UL)"PWM_CLK_DIV_4 (1UL)#PWM_CLK_DIV_8 (2UL)$PWM_CLK_DIV_16 (3UL)%PWM_EDGE_ALIGNED (0UL)&PWM_CENTER_ALIGNED (PWM_CTL_CNTTYPE_Msk)'PWM_TRIGGER_ADC_CNTR_IS_0 PWM_ADCTCTL0_ZPTRGEN0_Msk(PWM_TRIGGER_ADC_CNTR_IS_CMR_D PWM_ADCTCTL0_CDTRGEN0_Msk)PWM_TRIGGER_ADC_CNTR_IS_CNR PWM_ADCTCTL0_CPTRGEN0_Msk*PWM_TRIGGER_ADC_CNTR_IS_CMR_U PWM_ADCTCTL0_CUTRGEN0_Msk+PWM_FB0_EINT0 (PWM_BRKCTL_BRK0EN_Msk),PWM_FB0_ACMP1 (PWM_BRKCTL_BRK0EN_Msk | PWM_BRKCTL_BRK1SEL_Msk)-PWM_FB1_EINT1 (PWM_BRKCTL_BRK1EN_Msk).PWM_FB1_ACMP0 (PWM_BRKCTL_BRK1EN_Msk | PWM_BRKCTL_BRK0SEL_Msk)/PWM_PERIOD_INT_UNDERFLOW (0)0PWM_PERIOD_INT_MATCH_CNR (PWM_INTEN_PINTTYPE_Msk)4PWM_CH0 0x05PWM_CH1 0x16PWM_CH2 0x27PWM_CH3 0x38PWM_CH4 0x49PWM_CH5 0x5HPWM_ENABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL = (PWM->CTL & ~PWM_CTL_MODE_Msk) |(1UL << PWM_CTL_MODE_Pos))PPWM_DISABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_MODE_Msk)XPWM_ENABLE_GROUP_MODE(pwm) ((pwm)->CTL |= PWM_CTL_GROUPEN_Msk)`PWM_DISABLE_GROUP_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_GROUPEN_Msk)hPWM_ENABLE_SYNC_MODE(pwm) (PWM->CTL = ((pwm)->CTL & ~PWM_CTL_MODE_Msk) |(2UL << PWM_CTL_MODE_Pos))pPWM_DISABLE_SYNC_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_MODE_Msk)zPWM_ENABLE_OUTPUT_INVERTER(pwm,u32ChannelMask) do{ int i; (pwm)->CTL &= ~(PWM_CTL_PINV0_Msk|PWM_CTL_PINV1_Msk|PWM_CTL_PINV2_Msk|PWM_CTL_PINV3_Msk|PWM_CTL_PINV4_Msk|PWM_CTL_PINV5_Msk); for(i = 0; i < 6; i++) { if((u32ChannelMask) & (1 << i)) (pwm)->CTL |= (1 << (PWM_CTL_PINV0_Pos + (i * 4))); } }while(0)ŽPWM_SET_PRESCALER(pwm,u32ChannelNum,u32Prescaler) ((pwm)->CLKPSC = ((pwm)->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8)))žPWM_SET_DIVIDER(pwm,u32ChannelNum,u32Divider) ((pwm)->CLKDIV = ((pwm)->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << ((u32ChannelNum) * 4))) | ((u32Divider) << ((u32ChannelNum) * 4)))ªPWM_SET_CMR(pwm,u32ChannelNum,u32CMR) (*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + u32ChannelNum * 4)))= (u32CMR))PWM_SET_CNR(pwm,u32ChannelNum,u32CNR) (*((__IO uint32_t *) ((((uint32_t)&((pwm)->PERIOD0)) + (u32ChannelNum) * 4))) = (u32CNR))ÁPWM_SET_CMRD(pwm,u32ChannelNum,u32CMRD) (*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + (u32ChannelNum) * 4)))= (u32CMRD << 16))ÍPWM_SET_ALIGNED_TYPE(pwm,u32ChannelMask,u32AlignedType) ((pwm)->CTL = ((pwm)->CTL & ~PWM_CTL_CNTTYPE_Msk) | (u32AlignedType))ÖPWM_ENABLE_ASYMMETRIC_MODE(pwm) ((pwm)->CTL |= PWM_CTL_ASYMEN_Msk)ÞPWM_ENABLE_PCAEN(pwm) (PWM->PCACTL |= PWM_PCACTL_PCAEN_Msk)H<
..\..\..\Library\StdDriver\inc\pwm.hÈ
..\..\..\Library\StdDriver\inc\pwm.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] D:\WORK\Guitar\ChipTest\PAN159\PAN159-Template\SampleCode\Template\Keilpqr __SPI_H__  SPI_MODE_0 (SPI_CTL_TXNEG_Msk)!SPI_MODE_1 (SPI_CTL_RXNEG_Msk)"SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk)#SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk)%SPI_SLAVE (SPI_CTL_SLAVE_Msk)&SPI_MASTER (0x0)(SPI_SS (SPI_SSCTL_SS_Msk))SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk)*SPI_SS_ACTIVE_LOW (0x0),SPI_IE_MASK (0x01)-SPI_SSTA_INTEN_MASK (0x04).SPI_FIFO_TX_INTEN_MASK (0x08)/SPI_FIFO_RX_INTEN_MASK (0x10)0SPI_FIFO_RXOV_INTEN_MASK (0x20)1SPI_FIFO_TIMEOUT_INTEN_MASK (0x40)@SPI_ABORT_3WIRE_TRANSFER(spi) ( (spi)->SLVCTL |= SPI_SLVCTL_SLVABT_Msk )GSPI_CLR_3WIRE_START_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_SLVSTIF_Msk )NSPI_CLR_UNIT_TRANS_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_UNITIF_Msk )USPI_DISABLE_3WIRE_MODE(spi) ( (spi)->SLVCTL &= ~SPI_SLVCTL_SLV3WIRE_Msk )\SPI_ENABLE_3WIRE_MODE(spi) ( (spi)->SLVCTL |= SPI_SLVCTL_SLV3WIRE_Msk )cSPI_GET_RX_FIFO_COUNT(spi) ( (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos) & 0xf )lSPI_GET_RX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk) == SPI_STATUS_RXEMPTY_Msk ? 1:0 )uSPI_GET_TX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk) == SPI_STATUS_TXEMPTY_Msk ? 1:0 )~SPI_GET_TX_FIFO_FULL_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXFULL_Msk) == SPI_STATUS_TXFULL_Msk ? 1:0 )…SPI_READ_RX(spi) ( (spi)->RX )�SPI_WRITE_TX(spi,u32TxData) ( (spi)->TX = u32TxData )¬SPI_ENABLE_BYTE_REORDER(spi) ( (spi)->CTL |= SPI_CTL_REORDER_Msk )³SPI_DISABLE_BYTE_REORDER(spi) ( (spi)->CTL &= ~SPI_CTL_REORDER_Msk )»SPI_SET_SUSPEND_CYCLE(spi,u32SuspCycle) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | (u32SuspCycle << SPI_CTL_SUSPITV_Pos) )ÂSPI_SET_LSB_FIRST(spi) ( (spi)->CTL |= SPI_CTL_LSB_Msk )ÉSPI_SET_MSB_FIRST(spi) ( (spi)->CTL &= ~SPI_CTL_LSB_Msk )àSPI_IS_BUSY(spi) ( ((spi)->CTL & SPI_CTL_SPIEN_Msk) == SPI_CTL_SPIEN_Msk ? 1:0 )çSPI_TRIGGER(spi) ( (spi)->CTL |= SPI_CTL_SPIEN_Msk )H<
..\..\..\Library\StdDriver\inc\spi.hD
..\..\..\Library\StdDriver\inc\spi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] D:\WORK\Guitar\ChipTest\PAN159\PAN159-Template\SampleCode\Template\Keil<ë”SPI_SET_SS_HIGH$ëspi"·<‘ŸSPI_SET_SS_LOW$ëspi<ÄÑSPI_SET_DATA_WIDTH$ëspi$Yu32Widthtuv __TIMER_H__  TIMER_ONESHOT_MODE (0UL)!TIMER_PERIODIC_MODE (1UL << TIMER_CTL_OPMODE_Pos)"TIMER_TOGGLE_MODE (2UL << TIMER_CTL_OPMODE_Pos)#TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_OPMODE_Pos)$TIMER_CAPTURE_FREE_COUNTING_MODE (0UL)%TIMER_CAPTURE_TRIGGER_COUNTING_MODE (TIMER_EXTCTL_CAPSEL_Msk)&TIMER_CAPTURE_COUNTER_RESET_MODE (TIMER_EXTCTL_CAPFUNCS_Msk)'TIMER_CAPTURE_FALLING_EDGE (0UL)(TIMER_CAPTURE_RISING_EDGE (1UL << TIMER_EXTCTL_CAPEDGE_Pos))TIMER_CAPTURE_FALLING_THEN_RISING_EDGE (2UL << TIMER_EXTCTL_CAPEDGE_Pos)*TIMER_CAPTURE_RISING_THEN_FALLING_EDGE (3UL << TIMER_EXTCTL_CAPEDGE_Pos)+TIMER_COUNTER_RISING_EDGE (TIMER_EXTCTL_CNTPHASE_Msk),TIMER_COUNTER_FALLING_EDGE (0UL)-TIMER_TOGGLE_TMX_CNT_OUT (0UL).TIMER_TOGGLE_TMX_EXT (TIMER_CTL_TGLPINSEL_Msk)>TIMER_SET_CMP_VALUE(timer,u32Value) ((timer)->CMP = (u32Value))HTIMER_SET_PRESCALE_VALUE(timer,u32Value) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value))RTIMER_IS_ACTIVE(timer) ((timer)->CTL & TIMER_CTL_ACTSTS_Msk ? 1 : 0)]TIMER_SELECT_TOUT_PIN(timer,u32ToutSel) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLPINSEL_Msk) | (u32ToutSel))H>
..\..\..\Library\StdDriver\inc\timer.hd
..\..\..\Library\StdDriver\inc\timer.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] D:\WORK\Guitar\ChipTest\PAN159\PAN159-Template\SampleCode\Template\Keil<êfTIMER_Start$êtimer"Ó<�pTIMER_Stop$êtimer<²{TIMER_EnableWakeup$êtimer<Ù…TIMER_DisableWakeup$êtimer<ˆ�TIMER_EnableCaptureDebounce$êtimer<¸šTIMER_DisableCaptureDebounce$êtimer<ì¥TIMER_EnableEventCounterDebounce$êtimer<¡¯TIMER_DisableEventCounterDebounce$êtimer<ĹTIMER_EnableInt$êtimer<èÃTIMER_DisableInt$êtimer<’ÍTIMER_EnableCaptureInt$êtimer<½×TIMER_DisableCaptureInt$êtimer;öãTIMER_GetIntFlagY$êtimera__resultY<œíTIMER_ClearIntFlag$êtimer;ÜùTIMER_GetCaptureIntFlagY$êtimera__resultY<‰ƒTIMER_ClearCaptureIntFlag$êtimer;Å�TIMER_GetWakeupFlagY$êtimera__resultY<î™TIMER_ClearWakeupFlag$êtimer;«£TIMER_GetCaptureDataY$êtimera__resultY;ä­TIMER_GetCounterY$êtimera__resultYxyz{ __UART_H__ $UART_FIFO_RFITL_1BYTE (0x0 << UART_FIFO_RFITL_Pos)%UART_FIFO_RFITL_4BYTES (0x1 << UART_FIFO_RFITL_Pos)&UART_FIFO_RFITL_8BYTES (0x2 << UART_FIFO_RFITL_Pos)'UART_FIFO_RFITL_14BYTES (0x3 << UART_FIFO_RFITL_Pos))UART_FIFO_RTSTRGLV_1BYTE (0x0 << UART_FIFO_RTSTRGLV_Pos)*UART_FIFO_RTSTRGLV_4BYTES (0x1 << UART_FIFO_RTSTRGLV_Pos)+UART_FIFO_RTSTRGLV_8BYTES (0x2 << UART_FIFO_RTSTRGLV_Pos),UART_FIFO_RTSTRGLV_14BYTES (0x3 << UART_FIFO_RTSTRGLV_Pos)1UART_WORD_LEN_5 (0)2UART_WORD_LEN_6 (1)3UART_WORD_LEN_7 (2)4UART_WORD_LEN_8 (3)6UART_PARITY_NONE (0x0 << UART_LINE_PBE_Pos)7UART_PARITY_ODD (0x1 << UART_LINE_PBE_Pos)8UART_PARITY_EVEN (0x3 << UART_LINE_PBE_Pos)9UART_PARITY_MARK (0x5 << UART_LINE_PBE_Pos):UART_PARITY_SPACE (0x7 << UART_LINE_PBE_Pos)<UART_STOP_BIT_1 (0x0 << UART_LINE_NSB_Pos)=UART_STOP_BIT_1_5 (0x1 << UART_LINE_NSB_Pos)>UART_STOP_BIT_2 (0x1 << UART_LINE_NSB_Pos)DUART_RTS_IS_HIGH_LEV_TRG (0x1 << UART_MODEM_RTSACTLV_Pos)EUART_RTS_IS_LOW_LEV_TRG (0x0 << UART_MODEM_RTSACTLV_Pos)JUART_FUNC_SEL_UART (0x0 << UART_FUNSEL_FUN_SEL_Pos)KUART_FUNC_SEL_IrDA (0x2 << UART_FUNSEL_FUN_SEL_Pos)LUART_FUNC_SEL_RS485 (0x3 << UART_FUNSEL_FUN_SEL_Pos)^UART_BAUD_MODE0 (0)hUART_BAUD_MODE2 (UART_BAUD_BAUDM1_Msk | UART_BAUD_BAUDM0_Msk)tUART_BAUD_MODE0_DIVIDER(u32SrcFreq,u32BaudRate) (((u32SrcFreq + (u32BaudRate*8)) / u32BaudRate >> 4)-2)~UART_BAUD_MODE2_DIVIDER(u32SrcFreq,u32BaudRate) (((u32SrcFreq + (u32BaudRate/2)) / u32BaudRate)-2)‰UART_WRITE(uart,u8Data) (uart->DAT = (u8Data))’UART_READ(uart) (uart->DAT)œUART_GET_TX_EMPTY(uart) (uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk)¦UART_GET_RX_EMPTY(uart) (uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk)¯UART_IS_TX_EMPTY(uart) ((uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)¹UART_WAIT_TX_EMPTY(uart) while(!(((uart->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos))ÄUART_IS_RX_READY(uart) ((uart->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos)ÐUART_IS_TX_FULL(uart) ((uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos)ÜUART_IS_RX_FULL(uart) ((uart->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos)æUART_GET_TX_FULL(uart) (uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)ðUART_GET_RX_FULL(uart) (uart->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)ƒUART_ENABLE_INT(uart,u32eIntSel) (uart->INTEN |= (u32eIntSel))•UART_DISABLE_INT(uart,u32eIntSel) (uart->INTEN &= ~ (u32eIntSel))¯UART_GET_INT_FLAG(uart,u32eIntTypeFlag) ((uart->INTSTS & (u32eIntTypeFlag))?1:0)ÏUART_RS485_CLEAR_ADDR_FLAG(uart) (uart->FIFOSTS |= UART_FIFOSTS_ADDRDETF_Msk)ØUART_RS485_GET_ADDR_FLAG(uart) ((uart->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos)H=
..\..\..\Library\StdDriver\inc\uart.h
..\..\..\Library\StdDriver\inc\uart.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] D:\WORK\Guitar\ChipTest\PAN159\PAN159-Template\SampleCode\Template\Keil<ì¸UART_CLEAR_RTS$ìuart"ã<‘ÄUART_SET_RTS$ìuart2ËUART_CLEAR_RTSòUART_SET_RTS}~ __WDT_H__ WDT_TIMEOUT_2POW4 (0UL << WDT_CTL_TOUTSEL_Pos) WDT_TIMEOUT_2POW6 (1UL << WDT_CTL_TOUTSEL_Pos)!WDT_TIMEOUT_2POW8 (2UL << WDT_CTL_TOUTSEL_Pos)"WDT_TIMEOUT_2POW10 (3UL << WDT_CTL_TOUTSEL_Pos)#WDT_TIMEOUT_2POW12 (4UL << WDT_CTL_TOUTSEL_Pos)$WDT_TIMEOUT_2POW14 (5UL << WDT_CTL_TOUTSEL_Pos)%WDT_TIMEOUT_2POW16 (6UL << WDT_CTL_TOUTSEL_Pos)&WDT_TIMEOUT_2POW18 (7UL << WDT_CTL_TOUTSEL_Pos)(WDT_RESET_DELAY_3CLK (3UL << WDT_ALTCTL_RSTDSEL_Pos))WDT_RESET_DELAY_18CLK (2UL << WDT_ALTCTL_RSTDSEL_Pos)*WDT_RESET_DELAY_130CLK (1UL << WDT_ALTCTL_RSTDSEL_Pos)+WDT_RESET_DELAY_1026CLK (0UL << WDT_ALTCTL_RSTDSEL_Pos)9WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk)?WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk)EWDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk)NWDT_GET_RESET_FLAG() (WDT->CTL & WDT_CTL_RSTF_Msk ? 1 : 0)WWDT_GET_TIMEOUT_INT_FLAG() (WDT->CTL & WDT_CTL_IF_Msk ? 1 : 0)`WDT_GET_TIMEOUT_WAKEUP_FLAG() (WDT->CTL & WDT_CTL_WKF_Msk ? 1 : 0)hWDT_RESET_COUNTER() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk | WDT_CTL_RSTF_Msk)) | WDT_CTL_RSTCNT_Msk)H<
..\..\..\Library\StdDriver\inc\wdt.hÈ
..\..\..\Library\StdDriver\inc\wdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] D:\WORK\Guitar\ChipTest\PAN159\PAN159-Template\SampleCode\Template\Keil�‚ƒ __WWDT_H__ WWDT_PRESCALER_1 (0UL << WWDT_CTL_PSCSEL_Pos) WWDT_PRESCALER_2 (1UL << WWDT_CTL_PSCSEL_Pos)!WWDT_PRESCALER_4 (2UL << WWDT_CTL_PSCSEL_Pos)"WWDT_PRESCALER_8 (3UL << WWDT_CTL_PSCSEL_Pos)#WWDT_PRESCALER_16 (4UL << WWDT_CTL_PSCSEL_Pos)$WWDT_PRESCALER_32 (5UL << WWDT_CTL_PSCSEL_Pos)%WWDT_PRESCALER_64 (6UL << WWDT_CTL_PSCSEL_Pos)&WWDT_PRESCALER_128 (7UL << WWDT_CTL_PSCSEL_Pos)'WWDT_PRESCALER_192 (8UL << WWDT_CTL_PSCSEL_Pos)(WWDT_PRESCALER_256 (9UL << WWDT_CTL_PSCSEL_Pos))WWDT_PRESCALER_384 (0xAUL << WWDT_CTL_PSCSEL_Pos)*WWDT_PRESCALER_512 (0xBUL << WWDT_CTL_PSCSEL_Pos)+WWDT_PRESCALER_768 (0xCUL << WWDT_CTL_PSCSEL_Pos),WWDT_PRESCALER_1024 (0xDUL << WWDT_CTL_PSCSEL_Pos)-WWDT_PRESCALER_1536 (0xEUL << WWDT_CTL_PSCSEL_Pos).WWDT_PRESCALER_2048 (0xFUL << WWDT_CTL_PSCSEL_Pos)0WWDT_RELOAD_WORD (0x00005AA5)>WWDT_CLEAR_RESET_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTRF_Msk)FWWDT_CLEAR_INT_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTIF_Msk)OWWDT_GET_RESET_FLAG() (WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk ? 1 : 0)XWWDT_GET_INT_FLAG() (WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk ? 1 : 0)`WWDT_GET_COUNTER() (WWDT->CNT)kWWDT_RELOAD_COUNTER() (WWDT->RLDCNT = WWDT_RELOAD_WORD)H=
..\..\..\Library\StdDriver\inc\wwdt.hÌ
..\..\..\Library\StdDriver\inc\wwdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] D:\WORK\Guitar\ChipTest\PAN159\PAN159-Template\SampleCode\Template\Keil…†‡6__MINI58SERIES_H__ |__CM0_REV 0x0201}__NVIC_PRIO_BITS 2~__Vendor_SysTickConfig 0__MPU_PRESENT 0€__FPU_PRESENT 0…†‡‹ACMP_CTL_ACMPEN_Pos (0)ŒACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos)ŽACMP_CTL_ACMPIE_Pos (1)�ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos)‘ACMP_CTL_HYSSEL_Pos (2)’ACMP_CTL_HYSSEL_Msk (0x1ul << ACMP_CTL_HYSSEL_Pos)”ACMP_CTL_NEGSEL_Pos (4)•ACMP_CTL_NEGSEL_Msk (0x1ul << ACMP_CTL_NEGSEL_Pos)—ACMP_CTL_RTRGEN_Pos (8)˜ACMP_CTL_RTRGEN_Msk (0x1ul << ACMP_CTL_RTRGEN_Pos)šACMP_CTL_FTRGEN_Pos (9)›ACMP_CTL_FTRGEN_Msk (0x1ul << ACMP_CTL_FTRGEN_Pos)�ACMP_CTL_FILTSEL_Pos (20)žACMP_CTL_FILTSEL_Msk (0xful << ACMP_CTL_FILTSEL_Pos) ACMP_CTL_POSSEL_Pos (29)¡ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos)£ACMP_STATUS_ACMPIF0_Pos (0)¤ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos)¦ACMP_STATUS_ACMPIF1_Pos (1)§ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos)©ACMP_STATUS_ACMPO0_Pos (2)ªACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos)¬ACMP_STATUS_ACMPO1_Pos (3)­ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos)¯ACMP_VREF_CRVCTL_Pos (0)°ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos)²ACMP_VREF_IREFSEL_Pos (7)³ACMP_VREF_IREFSEL_Msk (0x1ul << ACMP_VREF_IREFSEL_Pos)•ADC_DAT_RESULT_Pos (0)–ADC_DAT_RESULT_Msk (0x3fful << ADC_DAT_RESULT_Pos)˜ADC_DAT_OV_Pos (16)™ADC_DAT_OV_Msk (0x1ul << ADC_DAT_OV_Pos)›ADC_DAT_VALID_Pos (17)œADC_DAT_VALID_Msk (0x1ul << ADC_DAT_VALID_Pos)žADC_CTL_ADCEN_Pos (0)ŸADC_CTL_ADCEN_Msk (0x1ul << ADC_CTL_ADCEN_Pos)¡ADC_CTL_ADCIEN_Pos (1)¢ADC_CTL_ADCIEN_Msk (0x1ul << ADC_CTL_ADCIEN_Pos)¤ADC_CTL_HWTRGSEL_Pos (4)¥ADC_CTL_HWTRGSEL_Msk (0x3ul << ADC_CTL_HWTRGSEL_Pos)§ADC_CTL_HWTRGCOND_Pos (6)¨ADC_CTL_HWTRGCOND_Msk (0x1ul << ADC_CTL_HWTRGCOND_Pos)ªADC_CTL_HWTRGEN_Pos (8)«ADC_CTL_HWTRGEN_Msk (0x1ul << ADC_CTL_HWTRGEN_Pos)­ADC_CTL_SWTRG_Pos (11)®ADC_CTL_SWTRG_Msk (0x1ul << ADC_CTL_SWTRG_Pos)°ADC_CHEN_CHEN0_Pos (0)±ADC_CHEN_CHEN0_Msk (0x1ul << ADC_CHEN_CHEN0_Pos)³ADC_CHEN_CHEN1_Pos (1)´ADC_CHEN_CHEN1_Msk (0x1ul << ADC_CHEN_CHEN1_Pos)ADC_CHEN_CHEN2_Pos (2)·ADC_CHEN_CHEN2_Msk (0x1ul << ADC_CHEN_CHEN2_Pos)¹ADC_CHEN_CHEN3_Pos (3)ºADC_CHEN_CHEN3_Msk (0x1ul << ADC_CHEN_CHEN3_Pos)¼ADC_CHEN_CHEN4_Pos (4)½ADC_CHEN_CHEN4_Msk (0x1ul << ADC_CHEN_CHEN4_Pos)¿ADC_CHEN_CHEN5_Pos (5)ÀADC_CHEN_CHEN5_Msk (0x1ul << ADC_CHEN_CHEN5_Pos)ÂADC_CHEN_CHEN6_Pos (6)ÃADC_CHEN_CHEN6_Msk (0x1ul << ADC_CHEN_CHEN6_Pos)ÅADC_CHEN_CHEN7_Pos (7)ÆADC_CHEN_CHEN7_Msk (0x1ul << ADC_CHEN_CHEN7_Pos)ÈADC_CHEN_CH7SEL_Pos (8)ÉADC_CHEN_CH7SEL_Msk (0x1ul << ADC_CHEN_CH7SEL_Pos)ËADC_CMP0_ADCMPEN_Pos (0)ÌADC_CMP0_ADCMPEN_Msk (0x1ul << ADC_CMP0_ADCMPEN_Pos)ÎADC_CMP0_ADCMPIE_Pos (1)ÏADC_CMP0_ADCMPIE_Msk (0x1ul << ADC_CMP0_ADCMPIE_Pos)ÑADC_CMP0_CMPCOND_Pos (2)ÒADC_CMP0_CMPCOND_Msk (0x1ul << ADC_CMP0_CMPCOND_Pos)ÔADC_CMP0_CMPCH_Pos (3)ÕADC_CMP0_CMPCH_Msk (0x7ul << ADC_CMP0_CMPCH_Pos)×ADC_CMP0_CMPMCNT_Pos (8)ØADC_CMP0_CMPMCNT_Msk (0xful << ADC_CMP0_CMPMCNT_Pos)ÚADC_CMP0_CMPDAT_Pos (16)ÛADC_CMP0_CMPDAT_Msk (0x3fful << ADC_CMP0_CMPDAT_Pos)ÝADC_CMP1_ADCMPEN_Pos (0)ÞADC_CMP1_ADCMPEN_Msk (0x1ul << ADC_CMP1_ADCMPEN_Pos)àADC_CMP1_ADCMPIE_Pos (1)áADC_CMP1_ADCMPIE_Msk (0x1ul << ADC_CMP1_ADCMPIE_Pos)ãADC_CMP1_CMPCOND_Pos (2)äADC_CMP1_CMPCOND_Msk (0x1ul << ADC_CMP1_CMPCOND_Pos)æADC_CMP1_CMPCH_Pos (3)çADC_CMP1_CMPCH_Msk (0x7ul << ADC_CMP1_CMPCH_Pos)éADC_CMP1_CMPMCNT_Pos (8)êADC_CMP1_CMPMCNT_Msk (0xful << ADC_CMP1_CMPMCNT_Pos)ìADC_CMP1_CMPDAT_Pos (16)íADC_CMP1_CMPDAT_Msk (0x3fful << ADC_CMP1_CMPDAT_Pos)ïADC_STATUS_ADIF_Pos (0)ðADC_STATUS_ADIF_Msk (0x1ul << ADC_STATUS_ADIF_Pos)òADC_STATUS_ADCMPF0_Pos (1)óADC_STATUS_ADCMPF0_Msk (0x1ul
CLK_CLKSEL1_PWMCH01SEL_Msk (0x3ul << CLK_CLKSEL1_PWMCH01SEL_Pos)‚
CLK_CLKSEL1_PWMCH23SEL_Pos (30)ƒ
CLK_CLKSEL1_PWMCH23SEL_Msk (0x3ul << CLK_CLKSEL1_PWMCH23SEL_Pos)…
CLK_CLKDIV_HCLKDIV_Pos (0)†
CLK_CLKDIV_HCLKDIV_Msk (0xful << CLK_CLKDIV_HCLKDIV_Pos)ˆ
CLK_CLKDIV_UARTDIV_Pos (8)‰
CLK_CLKDIV_UARTDIV_Msk (0xful << CLK_CLKDIV_UARTDIV_Pos)‹
CLK_CLKDIV_ADCDIV_Pos (16)Œ
CLK_CLKDIV_ADCDIV_Msk (0xfful << CLK_CLKDIV_ADCDIV_Pos)Ž
CLK_CLKSEL2_CLKOSEL_Pos (2)�
CLK_CLKSEL2_CLKOSEL_Msk (0x3ul << CLK_CLKSEL2_CLKOSEL_Pos)‘
CLK_CLKSEL2_PWMCH45SEL_Pos (4)’
CLK_CLKSEL2_PWMCH45SEL_Msk (0x3ul << CLK_CLKSEL2_PWMCH45SEL_Pos)”
CLK_CLKSEL2_WWDTSEL_Pos (16)•
CLK_CLKSEL2_WWDTSEL_Msk (0x3ul << CLK_CLKSEL2_WWDTSEL_Pos)—
CLK_PLLCTL_FBDIV_Pos (0)˜
CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos)š
CLK_PLLCTL_INDIV_Pos (9)›
CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos)�
CLK_PLLCTL_OUTDIV_Pos (14)ž
CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos) 
CLK_PLLCTL_PD_Pos (16)¡
CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos)£
CLK_PLLCTL_BP_Pos (17)¤
CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos)¦
CLK_PLLCTL_OE_Pos (18)§
CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos)©
CLK_PLLCTL_PLLSRC_Pos (19)ª
CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos)¬
CLK_CLKOCTL_FREQSEL_Pos (0)­
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