2021-10-07 09:32:05 +08:00
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Ø � \Ù ..\bsp.h מƊ ©ÙP D..\..\..\Library\Device\Nuvoton\Mini58Series\Include\Mini58Series.h �ÝõŠ \Ù6 *..\..\..\Library\CMSIS\Include\core_cm0.h åâÅŠ ·Ù9 -C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h üë�ö åÙ: ...\..\..\Library\CMSIS\Include\core_cmInstr.h åâÅŠ ÏÙ9 -..\..\..\Library\CMSIS\Include\cmsis_armcc.h åâÅŠ 5Ù9 -..\..\..\Library\CMSIS\Include\core_cmFunc.h åâÅŠ UÙW K..\..\..\Library\Device\Nuvoton\Mini58Series\Include\system_Mini58Series.h åâÅŠ -Ù1 %..\..\..\Library\StdDriver\inc\sys.h åâÅŠ ÜÙ1 %..\..\..\Library\StdDriver\inc\clk.h åâÅŠ Ù2 &..\..\..\Library\StdDriver\inc\acmp.h åâÅŠ ˜Ù1 %..\..\..\Library\StdDriver\inc\adc.h åâÅŠ Ù1 %..\..\..\Library\StdDriver\inc\fmc.h åâÅŠ Ù2 &..\..\..\Library\StdDriver\inc\gpio.h åâÅŠ ŠÙ1 %..\..\..\Library\StdDriver\inc\i2c.h åâÅŠ =Ù1 %..\..\..\Library\StdDriver\inc\pwm.h åâÅŠ çÙ1 %..\..\..\Library\StdDriver\inc\spi.h åâÅŠ ïÙ3 '..\..\..\Library\StdDriver\inc\timer.h åâÅŠ Ù2 &..\..\..\Library\StdDriver\inc\uart.h åâÅŠ }Ù1 %..\..\..\Library\StdDriver\inc\wdt.h åâÅŠ ìÙ2 &..\..\..\Library\StdDriver\inc\wwdt.h åâÅŠ sÙ ..\bsp.c îŸÆŠ —Ú P __BSP_H sÚ P __cplusplus
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2021-09-26 17:18:47 +08:00
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Ú P __MINI58SERIES_H__ Ú
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8" IRQn ]Ú " NonMaskableInt_IRQn ƒÚ " HardFault_IRQn ˆÚ " SVCall_IRQn äÚ " PendSV_IRQn ÙÚ "
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SysTick_IRQn =Ú " BOD_IRQn :Ú " WDT_IRQn Ú " EINT0_IRQn «Ú " EINT1_IRQn ªÚ " GPIO01_IRQn yÚ "
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GPIO234_IRQn ?Ú " PWM_IRQn Ú " FB_IRQn ‰Ú "
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TMR0_IRQn êÚ "
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TMR1_IRQn éÚ " UART0_IRQn ŸÚ " UART1_IRQn žÚ " SPI_IRQn #Ú " GPIO5_IRQn §Ú "
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HIRC_IRQn çÚ "
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I2C0_IRQn Ú "
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I2C1_IRQn Ú "
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ACMP_IRQn ìÚ "
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PDWU_IRQn ÍÚ " ADC_IRQn GÚ
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IRQn_Type ”Ú P
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__CM0_REV ïÚ P __NVIC_PRIO_BITS “Ú P __Vendor_SysTickConfig ôÚ P __MPU_PRESENT �Ú P __FPU_PRESENT ˆÚ P __ARMCC_VERSION Ú P __CORE_CM0_H_GENERIC šÚ P __stdint_h œÚ P __ARMCLIB_VERSION lÚ P __INT64_TYPE__ ;Ú P __INT64 ªÚ P __INT64_C_SUFFIX__ Ú P __PASTE2 NÚ P __PASTE ‚Ú P
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__INT64_C Ú P __UINT64_C Ú P __LONGLONG ™Ú P __STDINT_DECLS QÚ P __CLIBNS BÚ int8_t ŸÚ int16_t nÚ int32_t pÚ int64_t kÚ uint8_t (Ú uint16_t ÷Ú uint32_t ùÚ uint64_t ôÚ
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int_least8_t Ú int_least16_t êÚ int_least32_t ìÚ int_least64_t çÚ uint_least8_t ¤Ú uint_least16_t sÚ uint_least32_t uÚ uint_least64_t pÚ int_fast8_t ˆÚ
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int_fast16_t WÚ
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int_fast32_t YÚ
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int_fast64_t TÚ
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uint_fast8_t Ú uint_fast16_t àÚ uint_fast32_t âÚ uint_fast64_t ÝÚ P
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__sizeof_ptr ®Ú intptr_t }Ú
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uintptr_t Ú intmax_t �Ú
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uintmax_t Ú P INT8_MIN UÚ P
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INT16_MIN $Ú P
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INT32_MIN &Ú P
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INT64_MIN !Ú P INT8_MAX SÚ P
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INT16_MAX "Ú P
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INT32_MAX $Ú P
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INT64_MAX Ú P
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UINT8_MAX üÚ P UINT16_MAX ËÚ P UINT32_MAX ÍÚ P UINT64_MAX ÈÚ P INT_LEAST8_MIN qÚ P INT_LEAST16_MIN @Ú P INT_LEAST32_MIN BÚ P INT_LEAST64_MIN =Ú P INT_LEAST8_MAX oÚ P INT_LEAST16_MAX >Ú P INT_LEAST32_MAX @Ú P INT_LEAST64_MAX ;Ú P UINT_LEAST8_MAX Ú P UINT_LEAST16_MAX çÚ P UINT_LEAST32_MAX éÚ P UINT_LEAST64_MAX äÚ P INT_FAST8_MIN ¾Ú P INT_FAST16_MIN �Ú P INT_FAST32_MIN �Ú P INT_FAST64_MIN ŠÚ P INT_FAST8_MAX ¼Ú P INT_FAST16_MAX ‹Ú P INT_FAST32_MAX �Ú P INT_FAST64_MAX ˆÚ P UINT_FAST8_MAX eÚ P UINT_FAST16_MAX 4Ú P UINT_FAST32_MAX 6Ú P UINT_FAST64_MAX 1Ú P INTPTR_MIN “Ú P INTPTR_MAX ‘Ú P UINTPTR_MAX :Ú P INTMAX_MIN £Ú P INTMAX_MAX ¡Ú P UINTMAX_MAX JÚ P PTRDIFF_MIN cÚ P PTRDIFF_MAX aÚ P SIG_ATOMIC_MIN mÚ P SIG_ATOMIC_MAX kÚ P SIZE_MAX ;Ú P
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WCHAR_MIN Ú P
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WCHAR_MAX ÿÚ P WINT_MIN 6Ú P WINT_MAX 4Ú P INT8_C úÚ P INT16_C ÉÚ P INT32_C ËÚ P INT64_C ÆÚ P UINT8_C £Ú P UINT16_C rÚ P UINT32_C tÚ P UINT64_C oÚ P INTMAX_C HÚ P
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UINTMAX_C ñÚ! P __CM0_CMSIS_VERSION_MAIN 6Ú P __CM0_CMSIS_VERSION_SUB sÚ P __CM0_CMSIS_VERSION ÄÚ P __CORTEX_M xÚ P __CC_ARM 6Ú P __ASM "Ú P __INLINE >Ú P __STATIC_INLINE Ú P __FPU_USED ~Ú P __CORE_CMINSTR_H žÚ P __CMSIS_ARMCC_H Ú __get_CONTROL \Ú
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" —
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__regControl PÚ __set_CONTROL PÚ ,
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" ™control Ú
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" ™
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__regControl NÚ __get_IPSR EÚ
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" œ
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__regIPSR ôÚ __get_APSR MÚ
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" ž
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__regAPSR úÚ __get_xPSR Ú
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"
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__regXPSR áÚ
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__get_PSP ’Ú#
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" ¢__regProcessStackPointer XÚ
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__set_PSP †Ú ,
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" ¤topOfProcStack jÚ#
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" ¤__regProcessStackPointer VÚ
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__get_MSP •Ú
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" §__regMainStackPointer ³Ú
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__set_MSP ‰Ú ,
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" ©topOfMainStack tÚ
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" ©__regMainStackPointer ±Ú __get_PRIMASK fÚ
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" ¬
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__regPriMask eÚ __set_PRIMASK ZÚ ,
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" ®priMask )Ú
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" ®
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__regPriMask cÚ P __NOP Ú P __WFI Ú P __WFE !Ú P __SEV Ú P __ISB %Ú P __DSB *Ú P __DMB 0Ú P __REV Ú P __NO_EMBEDDED_ASM ƒÚ __REV16 ÔÚ ,
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" ºvalue ÛÚ __REVSH Ú ," ¼value ÛÚ P __ROR Ú P __BKPT ÐÚ __RBIT ùÚ ,
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" Àvalue ÕÚ
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" Àresult uÚ " Às Ú P __CLZ Ú P __CORE_CMFUNC_H Ú P __CMSIS_GENERIC Ú P __CORE_CM0_H_DEPENDANT Ú P __I ¾Ú P __O ¸Ú
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P __IO mÚ
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P __IM oÚ
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P __OM iÚ P __IOM Ú 8
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<unnamed> SÚ 8
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<unnamed> QÚ
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" Ï _reserved0 öÚ
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" ÏV ¡Ú
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" ÏC ´Ú
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" ÏZ �Ú
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" ÏN ©Ú " Îb „Ú
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" Îw �Ú
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APSR_Type ¸Ú P APSR_N_Pos CÚ P APSR_N_Msk JÚ P APSR_Z_Pos 7Ú P APSR_Z_Msk >Ú P APSR_C_Pos NÚ P APSR_C_Msk UÚ P APSR_V_Pos ;Ú P APSR_V_Msk BÚ 8
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<unnamed> SÚ 8
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<unnamed> QÚ
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" áISR óÚ
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" á _reserved0 äÚ " àb rÚ
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" àw oÚ
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IPSR_Type °Ú P
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IPSR_ISR_Pos —Ú P
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IPSR_ISR_Msk žÚ 8
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<unnamed> SÚ 8
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<unnamed> QÚ
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" êISR êÚ
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" ê _reserved0 ÛÚ
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" êT ˆÚ
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" ê _reserved1 ÚÚ
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" êV †Ú
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" êC ™Ú
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" êZ ‚Ú
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" êN ŽÚ " éb iÚ
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" éw fÚ
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xPSR_Type �Ú P xPSR_N_Pos Ú P xPSR_N_Msk Ú P xPSR_Z_Pos Ú P xPSR_Z_Msk Ú P xPSR_C_Pos Ú P xPSR_C_Msk Ú P xPSR_V_Pos Ú P xPSR_V_Msk Ú P xPSR_T_Pos Ú P xPSR_T_Msk
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Ú P
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xPSR_ISR_Pos hÚ P
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xPSR_ISR_Msk oÚ 8
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<unnamed> SÚ 8
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<unnamed> QÚ
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" ƒ _reserved0 AÚ
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" ƒSPSEL ³Ú
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" ƒ _reserved1 @Ú " ‚b ÏÚ
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" ‚w ÌÚ
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CONTROL_Type ÇÚ P CONTROL_SPSEL_Pos Ú P CONTROL_SPSEL_Msk Ú 8
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<unnamed> QÚ <" ŒISER ÎÚ <" |Œ
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RESERVED0 ïÚ <" ŒICER ÞÚ <" |Œ RSERVED1 5Ú <" ŒISPR ÃÚ <" |Œ
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RESERVED2 íÚ <" ŒICPR ÓÚ <" |Œ
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RESERVED3 ìÚ <" €Œ
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RESERVED4 äÚ
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<" ŒIP PÚ
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NVIC_Type ¾Ú 8
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<unnamed> QÚ
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" ˜CPUID °Ú
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" ˜ICSR öÚ
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" ˜
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RESERVED0 �Ú
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" ˜AIRCR ´Ú
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" ˜SCR AÚ
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" ˜CCR QÚ
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" ˜
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RESERVED1 ŒÚ <" ˜SHP Ú
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" ˜SHCSR ¢Ú SCB_Type Ú" P SCB_CPUID_IMPLEMENTER_Pos »Ú" P SCB_CPUID_IMPLEMENTER_Msk ÂÚ P SCB_CPUID_VARIANT_Pos ðÚ P SCB_CPUID_VARIANT_Msk ÷Ú# P SCB_CPUID_ARCHITECTURE_Pos xÚ# P SCB_CPUID_ARCHITECTURE_Msk Ú P SCB_CPUID_PARTNO_Pos 3Ú P SCB_CPUID_PARTNO_Msk :Ú P SCB_CPUID_REVISION_Pos ”Ú P SCB_CPUID_REVISION_Msk ›Ú P SCB_ICSR_NMIPENDSET_Pos NÚ P SCB_ICSR_NMIPENDSET_Msk UÚ P SCB_ICSR_PENDSVSET_Pos ‹Ú P SCB_ICSR_PENDSVSET_Msk ’Ú P SCB_ICSR_PENDSVCLR_Pos –Ú P SCB_ICSR_PENDSVCLR_Msk �Ú P SCB_ICSR_PENDSTSET_Pos �Ú P SCB_ICSR_PENDSTSET_Msk ”Ú P SCB_ICSR_PENDSTCLR_Pos ˜Ú P SCB_ICSR_PENDSTCLR_Msk ŸÚ P SCB_ICSR_ISRPREEMPT_Pos :Ú P SCB_ICSR_ISRPREEMPT_Msk AÚ P SCB_ICSR_ISRPENDING_Pos RÚ P SCB_ICSR_ISRPENDING_Msk YÚ! P SCB_ICSR_VECTPENDING_Pos Ú! P SCB_ICSR_VECTPENDING_Msk Ú P SCB_ICSR_VECTACTIVE_Pos WÚ P SCB_ICSR_VECTACTIVE_Msk ^Ú P SCB_AIRCR_VECTKEY_Pos îÚ P SCB_AIRCR_VECTKEY_Msk õÚ" P SCB_AIRCR_VECTKEYSTAT_Pos ªÚ" P SCB_AIRCR_VECTKEYSTAT_Msk ±Ú P SCB_AIRCR_ENDIANESS_Pos kÚ P SCB_AIRCR_ENDIANESS_Msk rÚ" P SCB_AIRCR_SYSRESETREQ_Pos —Ú" P SCB_AIRCR_SYSRESETREQ_Msk žÚ$ P SCB_AIRCR_VECTCLRACTIVE_Pos .Ú$ P SCB_AIRCR_VECTCLRACTIVE_Msk 5Ú P SCB_SCR_SEVONPEND_Pos àÚ P SCB_SCR_SEVONPEND_Msk çÚ P SCB_SCR_SLEEPDEEP_Pos ûÚ P SCB_SCR_SLEEPDEEP_Msk Ú P SCB_SCR_SLEEPONEXIT_Pos >Ú P SCB_SCR_SLEEPONEXIT_Msk EÚ P SCB_CCR_STKALIGN_Pos GÚ P SCB_CCR_STKALIGN_Msk NÚ P SCB_CCR_UNALIGN_TRP_Pos ;Ú P SCB_CCR_UNALIGN_TRP_Msk BÚ# P SCB_SHCSR_SVCALLPENDED_Pos xÚ# P SCB_SHCSR_SVCALLPENDED_Msk Ú 8
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<unnamed> QÚ
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" ÕCTRL µÚ
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" ÕLOAD ÊÚ
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" ÕVAL Ú
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" ÕCALIB �Ú
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SysTick_Type Ú# P SysTick_CTRL_COUNTFLAG_Pos ¦Ú# P SysTick_CTRL_COUNTFLAG_Msk Ú# P SysTick_CTRL_CLKSOURCE_Pos žÚ# P SysTick_CTRL_CLKSOURCE_Msk ¥Ú! P SysTick_CTRL_TICKINT_Pos 7Ú! P SysTick_CTRL_TICKINT_Msk >Ú P SysTick_CTRL_ENABLE_Pos ¨Ú P SysTick_CTRL_ENABLE_Msk ¯Ú P SysTick_LOAD_RELOAD_Pos Ú P SysTick_LOAD_RELOAD_Msk ´Ú P SysTick_VAL_CURRENT_Pos ~Ú P SysTick_VAL_CURRENT_Msk …Ú P SysTick_CALIB_NOREF_Pos ¯Ú P SysTick_CALIB_NOREF_Msk ¶Ú P SysTick_CALIB_SKEW_Pos ñÚ P SysTick_CALIB_SKEW_Msk øÚ P SysTick_CALIB_TENMS_Pos ¢Ú P SysTick_CALIB_TENMS_Msk ©Ú P _VAL2FLD qÚ P _FLD2VAL qÚ P SCS_BASE XÚ P
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SysTick_BASE oÚ P
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NVIC_BASE Ú P SCB_BASE iÚ P SCB íÚ P SysTick óÚ
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P NVIC “Ú P _BIT_SHIFT œÚ P _SHP_IDX -Ú P _IP_IDX �Ú NVIC_EnableIRQ Ú ,"" ùIRQn KÚ NVIC_DisableIRQ §Ú ,"" ûIRQn IÚ NVIC_GetPendingIRQ pÚ ,"" ýIRQn GÚ NVIC_SetPendingIRQ dÚ ,"" ÿIRQn EÚ NVIC_ClearPendingIRQ ¥Ú ,"" �IRQn ÂÚ NVIC_SetPriority ·Ú ,"" ƒIRQn ÀÚ ,
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" ƒ priority ¥Ú NVIC_GetPriority ÃÚ ,"" †IRQn ½Ú NVIC_SystemReset ½Ú __schedule_barrier sÚ __dsb çÚ __nop ÓÚ SysTick_Config YÚ ,
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" Œticks Ú" P __SYSTEM_MINI58SERIES_H__ ÍÚ P
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__XTAL12M Ú P
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__XTAL32K Ú P __IRC10K sÚ P __XTAL ÈÚ P __HXT Ú P __HIRC ÛÚ
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__HSI OÚ
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SystemCoreClock ãÚ
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CyclesPerUs “Ú
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PllClock ×Ú SystemCoreClockUpdate aÚ SystemInit »Ú 8
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<unnamed> QÚ <" ›CTL Ú
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" ›STATUS ;Ú
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" ›VREF ðÚ ACMP_T !Ú P ACMP_CTL_ACMPEN_Pos žÚ P ACMP_CTL_ACMPEN_Msk ¥Ú P ACMP_CTL_ACMPIE_Pos £Ú P ACMP_CTL_ACMPIE_Msk ªÚ P ACMP_CTL_HYSSEL_Pos zÚ P ACMP_CTL_HYSSEL_Msk �Ú P ACMP_CTL_NEGSEL_Pos ”Ú P ACMP_CTL_NEGSEL_Msk ›Ú P ACMP_CTL_RTRGEN_Pos €Ú P ACMP_CTL_RTRGEN_Msk ‡Ú P ACMP_CTL_FTRGEN_Pos ŒÚ P ACMP_CTL_FTRGEN_Msk “Ú P ACMP_CTL_FILTSEL_Pos =Ú P ACMP_CTL_FILTSEL_Msk DÚ P ACMP_CTL_POSSEL_Pos |Ú P ACMP_CTL_POSSEL_Msk ƒÚ P ACMP_STATUS_ACMPIF0_Pos iÚ P ACMP_STATUS_ACMPIF0_Msk pÚ P ACMP_STATUS_ACMPIF1_Pos hÚ P ACMP_STATUS_ACMPIF1_Msk oÚ P ACMP_STATUS_ACMPO0_Pos «Ú P ACMP_STATUS_ACMPO0_Msk ²Ú P ACMP_STATUS_ACMPO1_Pos ªÚ P ACMP_STATUS_ACMPO1_Msk ±Ú P ACMP_VREF_CRVCTL_Pos 2Ú P ACMP_VREF_CRVCTL_Msk 9Ú P ACMP_VREF_IREFSEL_Pos ôÚ P ACMP_VREF_IREFSEL_Msk ûÚ 8
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<unnamed> QÚ
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" ¼DAT +Ú <" ¼
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RESERVED0 Ú
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" ¼CTL !Ú
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" ¼CHEN äÚ
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" ¼CMP0 òÚ
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" ¼CMP1 ñÚ
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" ¼STATUS Ú <" ¼
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RESERVED1 )Ú
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" ¼TRGDLY (Ú
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" ¼EXTSMPT ÇÚ
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" ¼SEQCTL 2Ú
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" ¼SEQDAT1 Ú
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" ¼SEQDAT2 Ú ADC_T |Ú P ADC_DAT_RESULT_Pos ØÚ P ADC_DAT_RESULT_Msk ßÚ P ADC_DAT_OV_Pos Ú P ADC_DAT_OV_Msk !Ú P ADC_DAT_VALID_Pos IÚ P ADC_DAT_VALID_Msk PÚ P ADC_CTL_ADCEN_Pos TÚ P ADC_CTL_ADCEN_Msk [Ú P ADC_CTL_ADCIEN_Pos Ú P ADC_CTL_ADCIEN_Msk Ú P ADC_CTL_HWTRGSEL_Pos 9Ú P ADC_CTL_HWTRGSEL_Msk @Ú P ADC_CTL_HWTRGCOND_Pos ÷Ú P ADC_CTL_HWTRGCOND_Msk þÚ P ADC_CTL_HWTRGEN_Pos ŒÚ P ADC_CTL_HWTRGEN_Msk “Ú P ADC_CTL_SWTRG_Pos Ú P ADC_CTL_SWTRG_Msk Ú P ADC_CHEN_CHEN0_Pos $Ú P ADC_CHEN_CHEN0_Msk +Ú P ADC_CHEN_CHEN1_Pos #Ú P ADC_CHEN_CHEN1_Msk *Ú P ADC_CHEN_CHEN2_Pos "Ú P ADC_CHEN_CHEN2_Msk )Ú P ADC_CHEN_CHEN3_Pos !Ú P ADC_CHEN_CHEN3_Msk (Ú P ADC_CHEN_CHEN4_Pos Ú P ADC_CHEN_CHEN4_Msk 'Ú P ADC_CHEN_CHEN5_Pos Ú P ADC_CHEN_CHEN5_Msk &Ú P ADC_CHEN_CHEN6_Pos Ú P ADC_CHEN_CHEN6_Msk %Ú P ADC_CHEN_CHEN7_Pos Ú P ADC_CHEN_CHEN7_Msk $Ú P ADC_CHEN_CH7SEL_Pos ÊÚ P ADC_CHEN_CH7SEL_Msk ÑÚ P ADC_CMP0_ADCMPEN_Pos „Ú P ADC_CMP0_ADCMPEN_Msk ‹Ú P ADC_CMP0_ADCMPIE_Pos ‰Ú P ADC_CMP0_ADCMPIE_Msk �Ú P ADC_CMP0_CMPCOND_Pos xÚ P ADC_CMP0_CMPCOND_Msk Ú P ADC_CMP0_CMPCH_Pos Ú P ADC_CMP0_CMPCH_Msk Ú P ADC_CMP0_CMPMCNT_Pos jÚ P ADC_CMP0_CMPMCNT_Msk qÚ P ADC_CMP0_CMPDAT_Pos ÅÚ P ADC_CMP0_CMPDAT_Msk ÌÚ P ADC_CMP1_ADCMPEN_Pos ƒÚ P ADC_CMP1_ADCMPEN_Msk ŠÚ P ADC_CMP1_ADCMPIE_Pos ˆÚ P ADC_CMP1_ADCMPIE_Msk �Ú P ADC_CMP1_CMPCOND_Pos wÚ P ADC_CMP1_CMPCOND_Msk ~Ú P ADC_CMP1_CMPCH_Pos Ú P ADC_CMP1_CMPCH_Msk Ú P ADC_CMP1_CMPMCNT_Pos iÚ P ADC_CMP1_CMPMCNT_Msk pÚ P ADC_CMP1_CMPDAT_Pos ÄÚ P ADC_CMP1_CMPDAT_Msk ËÚ P ADC_STATUS_ADIF_Pos –Ú P ADC_STATUS_ADIF_Msk �Ú P ADC_STATUS_ADCMPF0_Pos ÉÚ P ADC_STATUS_ADCMPF0_Msk ÐÚ P ADC_STATUS_ADCMPF1_Pos ÈÚ P ADC_STATUS_ADCMPF1_Msk ÏÚ P ADC_STATUS_BUSY_Pos gÚ P ADC_STATUS_BUSY_Msk nÚ P ADC_STATUS_CHANNEL_Pos «Ú P ADC_STATUS_CHANNEL_Msk ²Ú P ADC_STATUS_VALID_Pos 8Ú P ADC_STATUS_VALID_Msk ?Ú P ADC_STATUS_OV_Pos Ú P ADC_STATUS_OV_Msk Ú P ADC_TRGDLY_DELAY_Pos GÚ P ADC_TRGDLY_DELAY_Msk NÚ P ADC_EXTSMPT_EXTSMPT_Pos Ú P ADC_EXTSMPT_EXTSMPT_Msk #Ú P ADC_SEQCTL_SEQEN_Pos DÚ P ADC_SEQCTL_SEQEN_Msk KÚ P ADC_SEQCTL_SEQTYPE_Pos ‘Ú P ADC_SEQCTL_SEQTYPE_Msk ˜Ú P ADC_SEQCTL_MODESEL_Pos ³Ú P ADC_SEQCTL_MODESEL_Msk ºÚ P ADC_SEQCTL_TRG1CTL_Pos »Ú P ADC_SEQCTL_TRG1CTL_Msk ÂÚ P ADC_SEQCTL_TRG2CTL_Pos ºÚ P ADC_SEQCTL_TRG2CTL_Msk ÁÚ P ADC_SEQDAT1_RESULT_Pos ¶Ú P ADC_SEQDAT1_RESULT_Msk ½Ú P ADC_SEQDAT1_OV_Pos øÚ P ADC_SEQDAT1_OV_Msk ÿÚ P ADC_SEQDAT1_VALID_Pos 'Ú P ADC_SEQDAT1_VALID_Msk .Ú P ADC_SEQDAT2_RESULT_Pos µÚ P ADC_SEQDAT2_RESULT_Msk ¼Ú P ADC_SEQDAT2_OV_Pos ÷Ú P ADC_SEQDAT2_OV_Msk þÚ P ADC_SEQDAT2_VALID_Pos &Ú P ADC_SEQDAT2_VALID_Msk -Ú 8
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<unnamed> QÚ
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" ¯PWRCTL .Ú
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" ¯AHBCLK eÚ
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" ¯APBCLK ]Ú
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" ¯STATUS &Ú
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" ¯CLKSEL0 Ú
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" ¯CLKSEL1 Ú
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" ¯CLKDIV MÚ
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" ¯CLKSEL2 Ú
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" ¯PLLCTL ?Ú
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" ¯CLKOCTL üÚ CLK_T jÚ P CLK_PWRCTL_XTLEN_Pos Ú P CLK_PWRCTL_XTLEN_Msk Ú P CLK_PWRCTL_HIRCEN_Pos ãÚ P CLK_PWRCTL_HIRCEN_Msk êÚ P CLK_PWRCTL_LIRCEN_Pos ßÚ P CLK_PWRCTL_LIRCEN_Msk æÚ P CLK_PWRCTL_PDWKDLY_Pos {Ú P CLK_PWRCTL_PDWKDLY_Msk ‚Ú P CLK_PWRCTL_PDWKIEN_Pos ˆÚ P CLK_PWRCTL_PDWKIEN_Msk �Ú P CLK_PWRCTL_PDWKIF_Pos ×Ú P CLK_PWRCTL_PDWKIF_Msk ÞÚ P CLK_PWRCTL_PDEN_Pos yÚ P CLK_PWRCTL_PDEN_Msk €Ú P CLK_PWRCTL_PDLXT_Pos Ú P CLK_PWRCTL_PDLXT_Msk Ú P CLK_AHBCLK_ISPCKEN_Pos ÄÚ P CLK_AHBCLK_ISPCKEN_Msk ËÚ P CLK_APBCLK_WDTCKEN_Pos ¹Ú P CLK_APBCLK_WDTCKEN_Msk ÀÚ P CLK_APBCLK_TMR0CKEN_Pos ƒÚ P CLK_APBCLK_TMR0CKEN_Msk ŠÚ P CLK_APBCLK_TMR1CKEN_Pos ‚Ú P CLK_APBCLK_TMR1CKEN_Msk ‰Ú P CLK_APBCLK_CLKOCKEN_Pos }Ú P CLK_APBCLK_CLKOCKEN_Msk „Ú P CLK_APBCLK_I2C0CKEN_Pos ¸Ú P CLK_APBCLK_I2C0CKEN_Msk ¿Ú P CLK_APBCLK_I2C1CKEN_Pos ·Ú P CLK_APBCLK_I2C1CKEN_Msk ¾Ú P CLK_APBCLK_SPICKEN_Pos ¼Ú P CLK_APBCLK_SPICKEN_Msk ÃÚ! P CLK_APBCLK_UART0CKEN_Pos 8Ú! P CLK_APBCLK_UART0CKEN_Msk ?Ú! P CLK_APBCLK_UART1CKEN_Pos 7Ú! P CLK_APBCLK_UART1CKEN_Msk >Ú# P CLK_APBCLK_PWMCH01CKEN_Pos ÀÚ# P CLK_APBCLK_PWMCH01CKEN_Msk ÇÚ# P CLK_APBCLK_PWMCH23CKEN_Pos ¼Ú# P CLK_APBCLK_PWMCH23CKEN_Msk ÃÚ# P CLK_APBCLK_PWMCH45CKEN_Pos ¸Ú# P CLK_APBCLK_PWMCH45CKEN_Msk ¿Ú P CLK_APBCLK_ADCCKEN_Pos àÚ P CLK_APBCLK_ADCCKEN_Msk çÚ P CLK_APBCLK_ACMPCKEN_Pos …Ú P CLK_APBCLK_ACMPCKEN_Msk ŒÚ P CLK_STATUS_XTLSTB_Pos ³Ú P CLK_STATUS_XTLSTB_Msk ºÚ P CLK_STATUS_PLLSTB_Pos ÃÚ P CLK_STATUS_PLLSTB_Msk ÊÚ P CLK_STATUS_LIRCSTB_Pos Ú P CLK_STATUS_LIRCSTB_Msk †Ú P CLK_STATUS_HIRCSTB_Pos ƒÚ P CLK_STATUS_HIRCSTB_Msk ŠÚ P CLK_STATUS_CLKSFAIL_Pos GÚ P CLK_STATUS_CLKSFAIL_Msk NÚ P CLK_CLKSEL0_HCLKSEL_Pos €Ú P CLK_CLKSEL0_HCLKSEL_Msk ‡Ú! P CLK_CLKSEL0_STCLKSEL_Pos Ú! P CLK_CLKSEL0_STCLKSEL_Msk &Ú P CLK_CLKSEL1_WDTSEL_Pos ´Ú P CLK_CLKSEL1_WDTSEL_Msk »Ú P CLK_CLKSEL1_ADCSEL_Pos ÛÚ P CLK_CLKSEL1_ADCSEL_Msk âÚ P CLK_CLKSEL1_SPISEL_Pos ·Ú P CLK_CLKSEL1_SPISEL_Msk ¾Ú P CLK_CLKSEL1_TMR0SEL_Pos ~Ú P CLK_CLKSEL1_TMR0SEL_Msk …Ú P CLK_CLKSEL1_TMR1SEL_Pos }Ú P CLK_CLKSEL1_TMR1SEL_Msk „Ú P CLK_CLKSEL1_UARTSEL_Pos eÚ P CLK_CLKSEL1_UARTSEL_Msk lÚ# P CLK_CLKSEL1_PWMCH01SEL_Pos »Ú# P CLK_CLKSEL1_PWMCH01SEL_Msk ÂÚ# P CLK_CLKSEL1_PWMCH23SEL_Pos ·Ú# P CLK_CLKSEL1_PWMCH23SEL_Msk ¾Ú P CLK_CLKDIV_HCLKDIV_Pos ´Ú P CLK_CLKDIV_HCLKDIV_Msk »Ú P CLK_CLKDIV_UARTDIV_Pos šÚ P CLK_CLKDIV_UARTDIV_Msk ¡Ú P CLK_CLKDIV_ADCDIV_Pos Ú P CLK_CLKDIV_ADCDIV_Msk Ú P CLK_CLKSEL2_CLKOSEL_Pos wÚ P CLK_CLKSEL2_CLKOSEL_Msk ~Ú# P CLK_CLKSEL2_PWMCH45SEL_Pos ²Ú# P CLK_CLKSEL2_PWMCH45SEL_Msk ¹Ú P CLK_CLKSEL2_WWDTSEL_Pos ZÚ P CLK_CLKSEL2_WWDTSEL_Msk aÚ P CLK_PLLCTL_FBDIV_Pos DÚ P CLK_PLLCTL_FBDIV_Msk KÚ P CLK_PLLCTL_INDIV_Pos 5Ú P CLK_PLLCTL_INDIV_Msk <Ú P CLK_PLLCTL_OUTDIV_Pos ÒÚ P CLK_PLLCTL_OUTDIV_Msk ÙÚ P CLK_PLLCTL_PD_Pos !Ú P CLK_PLLCTL_PD_Msk (Ú P CLK_PLLCTL_BP_Pos #Ú P CLK_PLLCTL_BP_Msk *Ú P CLK_PLLCTL_OE_Pos !Ú P CLK_PLLCTL_OE_Msk (Ú P CLK_PLLCTL_PLLSRC_Pos ÝÚ P CLK_PLLCTL_PLLSRC_Msk äÚ P CLK_CLKOCTL_FREQSEL_Pos VÚ P CLK_CLKOCTL_FREQSEL_Msk ]Ú P CLK_CLKOCTL_CLKOEN_Pos ®Ú P CLK_CLKOCTL_CLKOEN_Msk µÚ P CLK_CLKOCTL_DIV1EN_Pos ÃÚ P CLK_CLKOCTL_DIV1EN_Msk ÊÚ 8
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<unnamed> QÚ
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" §ISPCTL BÚ
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" §ISPADDR Ú
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" §ISPDAT LÚ
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" §ISPCMD QÚ
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" §ISPTRG 8Ú
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" §DFBA Ú
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" §FATCTL SÚ <" $§
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RESERVED0 )Ú
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" §ISPSTS +Ú FMC_T nÚ P FMC_ISPCTL_ISPEN_Pos 0Ú P FMC_ISPCTL_ISPEN_Msk 7Ú P FMC_ISPCTL_BS_Pos Ú P FMC_ISPCTL_BS_Msk 'Ú P FMC_ISPCTL_SPUEN_Pos $Ú P FMC_ISPCTL_SPUEN_Msk +Ú P FMC_ISPCTL_APUEN_Pos 6Ú P FMC_ISPCTL_APUEN_Msk =Ú P FMC_ISPCTL_CFGUEN_Pos õÚ P FMC_ISPCTL_CFGUEN_Msk üÚ P FMC_ISPCTL_LDUEN_Pos 7Ú P FMC_ISPCTL_LDUEN_Msk >Ú P FMC_ISPCTL_ISPFF_Pos 7Ú P FMC_ISPCTL_ISPFF_Msk >Ú P FMC_ISPADDR_ISPADDR_Pos jÚ P FMC_ISPADDR_ISPADDR_Msk qÚ P FMC_ISPDAT_ISPDAT_Pos òÚ P FMC_ISPDAT_ISPDAT_Msk ùÚ P FMC_ISPCMD_CMD_Pos îÚ P FMC_ISPCMD_CMD_Msk õÚ P FMC_ISPTRG_ISPGO_Pos #Ú P FMC_ISPTRG_ISPGO_Msk *Ú P FMC_DFBA_DFBA_Pos jÚ P FMC_DFBA_DFBA_Msk qÚ P FMC_FATCTL_FOM_Pos âÚ P FMC_FATCTL_FOM_Msk éÚ P FMC_ISPSTS_ISPBUSY_Pos eÚ P FMC_ISPSTS_ISPBUSY_Msk lÚ P FMC_ISPSTS_CBS_Pos ÄÚ P FMC_ISPSTS_CBS_Msk ËÚ P FMC_ISPSTS_ISPFF_Pos Ú P FMC_ISPSTS_ISPFF_Msk 'Ú P FMC_ISPSTS_VECMAP_Pos ÚÚ P FMC_ISPSTS_VECMAP_Msk áÚ P FMC_ISPSTS_SCODE_Pos *Ú P FMC_ISPSTS_SCODE_Msk 1Ú 8
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<unnamed> QÚ
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" ÖMODE ÁÚ
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" ÖDINOFF ,Ú
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" ÖDOUT ªÚ
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" ÖDATMSK Ú
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" ÖPIN Ú
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" ÖDBEN ÍÚ
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" ÖINTTYPE ³Ú
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" ÖINTEN fÚ
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" ÖINTSRC Ú GPIO_T Ú 8
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<unnamed> QÚ
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" áDBCTL pÚ
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GPIO_DB_T (Ú P GP_MODE_MODE0_Pos IÚ P GP_MODE_MODE0_Msk PÚ P GP_MODE_MODE1_Pos HÚ P GP_MODE_MODE1_Msk OÚ P GP_MODE_MODE2_Pos GÚ P GP_MODE_MODE2_Msk NÚ P GP_MODE_MODE3_Pos FÚ P GP_MODE_MODE3_Msk MÚ P GP_MODE_MODE4_Pos EÚ P GP_MODE_MODE4_Msk LÚ P GP_MODE_MODE5_Pos DÚ P GP_MODE_MODE5_Msk KÚ P GP_DINOFF_DINOFF0_Pos Ú P GP_DINOFF_DINOFF0_Msk &Ú P GP_DINOFF_DINOFF1_Pos Ú P GP_DINOFF_DINOFF1_Msk %Ú P GP_DINOFF_DINOFF2_Pos Ú P GP_DINOFF_DINOFF2_Msk $Ú P GP_DINOFF_DINOFF3_Pos Ú P GP_DINOFF_DINOFF3_Msk #Ú P GP_DINOFF_DINOFF4_Pos Ú P GP_DINOFF_DINOFF4_Msk "Ú P GP_DINOFF_DINOFF5_Pos Ú P GP_DINOFF_DINOFF5_Msk !Ú P GP_DINOFF_DINOFF6_Pos Ú P GP_DINOFF_DINOFF6_Msk Ú P GP_DINOFF_DINOFF7_Pos Ú P GP_DINOFF_DINOFF7_Msk Ú P GP_DOUT_DOUT0_Pos Ú P GP_DOUT_DOUT0_Msk "Ú P GP_DOUT_DOUT1_Pos Ú P GP_DOUT_DOUT1_Msk !Ú P GP_DOUT_DOUT2_Pos Ú P GP_DOUT_DOUT2_Msk Ú P GP_DOUT_DOUT3_Pos Ú P GP_DOUT_DOUT3_Msk Ú P GP_DOUT_DOUT4_Pos Ú P GP_DOUT_DOUT4_Msk Ú P GP_DOUT_DOUT5_Pos Ú P GP_DOUT_DOUT5_Msk Ú P GP_DOUT_DOUT6_Pos Ú P GP_DOUT_DOUT6_Msk Ú P GP_DOUT_DOUT7_Pos Ú P GP_DOUT_DOUT7_Msk Ú P GP_DATMSK_DATMSK0_Pos Ú P GP_DATMSK_DATMSK0_Msk
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Ú P GP_DATMSK_DATMSK1_Pos Ú P GP_DATMSK_DATMSK1_Msk Ú P GP_DATMSK_DATMSK2_Pos Ú P GP_DATMSK_DATMSK2_Msk Ú P GP_DATMSK_DATMSK3_Pos Ú P GP_DATMSK_DATMSK3_Msk Ú P GP_DATMSK_DATMSK4_Pos ÿÚ P GP_DATMSK_DATMSK4_Msk Ú P GP_DATMSK_DATMSK5_Pos þÚ P GP_DATMSK_DATMSK5_Msk Ú P GP_DATMSK_DATMSK6_Pos ýÚ P GP_DATMSK_DATMSK6_Msk Ú P GP_DATMSK_DATMSK7_Pos üÚ P GP_DATMSK_DATMSK7_Msk Ú P GP_PIN_PIN0_Pos ÉÚ P GP_PIN_PIN0_Msk ÐÚ P GP_PIN_PIN1_Pos ÈÚ P GP_PIN_PIN1_Msk ÏÚ P GP_PIN_PIN2_Pos ÇÚ P GP_PIN_PIN2_Msk ÎÚ P GP_PIN_PIN3_Pos ÆÚ P GP_PIN_PIN3_Msk ÍÚ P GP_PIN_PIN4_Pos ÅÚ P GP_PIN_PIN4_Msk ÌÚ P GP_PIN_PIN5_Pos ÄÚ P GP_PIN_PIN5_Msk ËÚ P GP_PIN_PIN6_Pos ÃÚ P GP_PIN_PIN6_Msk ÊÚ P GP_PIN_PIN7_Pos ÂÚ P GP_PIN_PIN7_Msk ÉÚ P GP_DBEN_DBEN0_Pos aÚ P GP_DBEN_DBEN0_Msk hÚ P GP_DBEN_DBEN1_Pos `Ú P GP_DBEN_DBEN1_Msk gÚ P GP_DBEN_DBEN2_Pos _Ú P GP_DBEN_DBEN2_Msk fÚ P GP_DBEN_DBEN3_Pos ^Ú P GP_DBEN_DBEN3_Msk eÚ P GP_DBEN_DBEN4_Pos ]Ú P GP_DBEN_DBEN4_Msk dÚ P GP_DBEN_DBEN5_Pos \Ú P GP_DBEN_DBEN5_Msk cÚ P GP_DBEN_DBEN6_Pos [Ú P GP_DBEN_DBEN6_Msk bÚ P GP_DBEN_DBEN7_Pos ZÚ P GP_DBEN_DBEN7_Msk aÚ P GP_INTTYPE_TYPE0_Pos Ú P GP_INTTYPE_TYPE0_Msk %Ú P GP_INTTYPE_TYPE1_Pos Ú P GP_INTTYPE_TYPE1_Msk $Ú P GP_INTTYPE_TYPE2_Pos Ú P GP_INTTYPE_TYPE2_Msk #Ú P GP_INTTYPE_TYPE3_Pos Ú P GP_INTTYPE_TYPE3_Msk "Ú P GP_INTTYPE_TYPE4_Pos Ú P GP_INTTYPE_TYPE4_Msk !Ú P GP_INTTYPE_TYPE5_Pos Ú P GP_INTTYPE_TYPE5_Msk Ú P GP_INTTYPE_TYPE6_Pos Ú P GP_INTTYPE_TYPE6_Msk Ú P GP_INTTYPE_TYPE7_Pos Ú P GP_INTTYPE_TYPE7_Msk Ú P GP_INTEN_FLIEN0_Pos £Ú P GP_INTEN_FLIEN0_Msk ªÚ P GP_INTEN_FLIEN1_Pos ¢Ú P GP_INTEN_FLIEN1_Msk ©Ú P GP_INTEN_FLIEN2_Pos ¡Ú P GP_INTEN_FLIEN2_Msk ¨Ú P GP_INTEN_FLIEN3_Pos Ú P GP_INTEN_FLIEN3_Msk §Ú P GP_INTEN_FLIEN4_Pos ŸÚ P GP_INTEN_FLIEN4_Msk ¦Ú P GP_INTEN_FLIEN5_Pos žÚ P GP_INTEN_FLIEN5_Msk ¥Ú P GP_INTEN_FLIEN6_Pos �Ú P GP_INTEN_FLIEN6_Msk ¤Ú P GP_INTEN_FLIEN7_Pos œÚ P GP_INTEN_FLIEN7_Msk £Ú P GP_INTEN_RHIEN0_Pos ›Ú P GP_INTEN_RHIEN0_Msk ¢Ú P GP_INTEN_RHIEN1_Pos šÚ P GP_INTEN_RHIEN1_Msk ¡Ú P GP_INTEN_RHIEN2_Pos ™Ú P GP_INTEN_RHIEN2_Msk Ú P GP_INTEN_RHIEN3_Pos ˜Ú P GP_INTEN_RHIEN3_Msk ŸÚ P GP_INTEN_RHIEN4_Pos —Ú P GP_INTEN_RHIEN4_Msk žÚ P GP_INTEN_RHIEN5_Pos –Ú P GP_INTEN_RHIEN5_Msk �Ú P GP_INTEN_RHIEN6_Pos •Ú P GP_INTEN_RHIEN6_Msk œÚ P GP_INTEN_RHIEN7_Pos ”Ú P GP_INTEN_RHIEN7_Msk ›Ú P GP_INTSRC_INTSRC0_Pos åÚ P GP_INTSRC_INTSRC0_Msk ìÚ P GP_INTSRC_INTSRC1_Pos äÚ P GP_INTSRC_INTSRC1_Msk ëÚ P GP_INTSRC_INTSRC2_Pos ãÚ P GP_INTSRC_INTSRC2_Msk êÚ P GP_INTSRC_INTSRC3_Pos âÚ P GP_INTSRC_INTSRC3_Msk éÚ P GP_INTSRC_INTSRC4_Pos áÚ P GP_INTSRC_INTSRC4_Msk èÚ P GP_INTSRC_INTSRC5_Pos àÚ P GP_INTSRC_INTSRC5_Msk çÚ P GP_INTSRC_INTSRC6_Pos ßÚ P GP_INTSRC_INTSRC6_Msk æÚ P GP_INTSRC_INTSRC7_Pos ÞÚ P GP_INTSRC_INTSRC7_Msk åÚ P GP_INTSRC_INTSRC8_Pos ÝÚ P GP_INTSRC_INTSRC8_Msk äÚ P GP_INTSRC_INTSRC9_Pos ÜÚ P GP_INTSRC_INTSRC9_Msk ãÚ P GP_INTSRC_INTSRC10_Pos ²Ú P GP_INTSRC_INTSRC10_Msk ¹Ú P GP_INTSRC_INTSRC11_Pos ±Ú P GP_INTSRC_INTSRC11_Msk ¸Ú P GP_INTSRC_INTSRC12_Pos °Ú P GP_INTSRC_INTSRC12_Msk ·Ú P GP_INTSRC_INTSRC13_Pos ¯Ú P GP_INTSRC_INTSRC13_Msk ¶Ú P GP_INTSRC_INTSRC14_Pos ®Ú P GP_INTSRC_INTSRC14_Msk µÚ P GP_INTSRC_INTSRC15_Pos Ú P GP_INTSRC_INTSRC15_Msk ´Ú P GP_DBCTL_DBCLKSEL_Pos Ú P GP_DBCTL_DBCLKSEL_Msk Ú P GP_DBCTL_DBCLKSRC_Pos
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Ú P GP_DBCTL_DBCLKSRC_Msk Ú P GP_DBCTL_ICLKON_Pos –Ú P GP_DBCTL_ICLKON_Msk �Ú 8
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<unnamed> QÚ
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" –CTL CÚ
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" –ADDR0 ×Ú
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" –DAT MÚ
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" –STATUS <Ú
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" –CLKDIV cÚ
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" –TOCTL œÚ
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" –ADDR1 ÖÚ
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" –ADDR2 ÕÚ
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" –ADDR3 ÔÚ
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" – ADDRMSK0 æÚ
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" – ADDRMSK1 åÚ
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" – ADDRMSK2 äÚ
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" – ADDRMSK3 ãÚ <" –
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RESERVED0 TÚ
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" –CTL1 Ú
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" –STATUS1 Ú I2C_T †Ú P I2C_CTL_AA_Pos =Ú P I2C_CTL_AA_Msk DÚ P I2C_CTL_SI_Pos #Ú P I2C_CTL_SI_Msk *Ú P I2C_CTL_STO_Pos ÇÚ P I2C_CTL_STO_Msk ÎÚ P I2C_CTL_STA_Pos ÕÚ P I2C_CTL_STA_Msk ÜÚ P I2C_CTL_I2CEN_Pos hÚ P I2C_CTL_I2CEN_Msk oÚ P I2C_CTL_INTEN_Pos ;Ú P I2C_CTL_INTEN_Msk BÚ P I2C_ADDR0_GC_Pos ÉÚ P I2C_ADDR0_GC_Msk ÐÚ P I2C_ADDR0_ADDR_Pos 4Ú P I2C_ADDR0_ADDR_Msk ;Ú P I2C_DAT_DAT_Pos îÚ P I2C_DAT_DAT_Msk õÚ P I2C_STATUS_STATUS_Pos ÌÚ P I2C_STATUS_STATUS_Msk ÓÚ P I2C_CLKDIV_DIVIDER_Pos ÎÚ P I2C_CLKDIV_DIVIDER_Msk ÕÚ P I2C_TOCTL_TOIF_Pos âÚ P I2C_TOCTL_TOIF_Msk éÚ P I2C_TOCTL_TOCURIEN_Pos £Ú P I2C_TOCTL_TOCURIEN_Msk ªÚ P I2C_TOCTL_TOCEN_Pos ™Ú P I2C_TOCTL_TOCEN_Msk Ú P I2C_ADDR1_GC_Pos ÈÚ P I2C_ADDR1_GC_Msk ÏÚ P I2C_ADDR1_ADDR_Pos 3Ú P I2C_ADDR1_ADDR_Msk :Ú P I2C_ADDR2_GC_Pos ÇÚ P I2C_ADDR2_GC_Msk ÎÚ P I2C_ADDR2_ADDR_Pos 2Ú P I2C_ADDR2_ADDR_Msk 9Ú P I2C_ADDR3_GC_Pos ÆÚ P I2C_ADDR3_GC_Msk ÍÚ P I2C_ADDR3_ADDR_Pos 1Ú P I2C_ADDR3_ADDR_Msk 8Ú! P I2C_ADDRMSK0_ADDRMSK_Pos RÚ! P I2C_ADDRMSK0_ADDRMSK_Msk YÚ! P I2C_ADDRMSK1_ADDRMSK_Pos QÚ! P I2C_ADDRMSK1_ADDRMSK_Msk XÚ! P I2C_ADDRMSK2_ADDRMSK_Pos PÚ! P I2C_ADDRMSK2_ADDRMSK_Msk WÚ! P I2C_ADDRMSK3_ADDRMSK_Pos OÚ! P I2C_ADDRMSK3_ADDRMSK_Msk VÚ P I2C_CTL1_WKEN_Pos SÚ P I2C_CTL1_WKEN_Msk ZÚ P I2C_CTL1_TWOLVFIFO_Pos ¾Ú P I2C_CTL1_TWOLVFIFO_Msk ÅÚ P I2C_CTL1_NSTRETCH_Pos Ú P I2C_CTL1_NSTRETCH_Msk Ú P I2C_CTL1_OVIEN_Pos Ú P I2C_CTL1_OVIEN_Msk Ú P I2C_CTL1_URIEN_Pos Ú P I2C_CTL1_URIEN_Msk
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Ú P I2C_STATUS1_WKIF_Pos PÚ P I2C_STATUS1_WKIF_Msk WÚ P I2C_STATUS1_FULL_Pos NÚ P I2C_STATUS1_FULL_Msk UÚ P I2C_STATUS1_EMPTY_Pos ðÚ P I2C_STATUS1_EMPTY_Msk ÷Ú P I2C_STATUS1_OVIF_Pos MÚ P I2C_STATUS1_OVIF_Msk TÚ P I2C_STATUS1_URIF_Pos KÚ P I2C_STATUS1_URIF_Msk RÚ 8
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<unnamed> QÚ
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" ì IRQ0_SRC cÚ
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" ì IRQ1_SRC bÚ
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" ì IRQ2_SRC aÚ
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" ì IRQ3_SRC `Ú
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" ì IRQ4_SRC _Ú
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" ì IRQ5_SRC ^Ú
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" ì IRQ6_SRC ]Ú
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" ì IRQ7_SRC \Ú
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" ì IRQ8_SRC [Ú
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" ì IRQ9_SRC ZÚ <" ì RESERVE0 DÚ
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" ì
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IRQ12_SRC .Ú
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" ì
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IRQ13_SRC -Ú
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" ì
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IRQ14_SRC ,Ú <" ì RESERVE1 GÚ
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" ì
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IRQ16_SRC *Ú
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" ì
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IRQ17_SRC )Ú
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" ì
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IRQ18_SRC (Ú
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" ì
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IRQ19_SRC 'Ú <" ì RESERVE2 6Ú
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" ì
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IRQ25_SRC *Ú <" ì RESERVE3 AÚ
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" ì
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IRQ28_SRC 'Ú
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" ì
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IRQ29_SRC &Ú
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" ìCON ðÚ
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" ìIRQ äÚ INTR_T Ú! P INT_IRQ0_SRC_BOD_INT_Pos ßÚ! P INT_IRQ0_SRC_BOD_INT_Msk æÚ! P INT_IRQ1_SRC_WDT_INT_Pos ÄÚ! P INT_IRQ1_SRC_WDT_INT_Msk ËÚ" P INT_IRQ1_SRC_WWDT_INT_Pos kÚ" P INT_IRQ1_SRC_WWDT_INT_Msk rÚ P INT_IRQ2_SRC_EINT0_Pos Ú P INT_IRQ2_SRC_EINT0_Msk §Ú P INT_IRQ3_SRC_EINT1_Pos žÚ P INT_IRQ3_SRC_EINT1_Msk ¥Ú! P INT_IRQ4_SRC_GP0_INT_Pos éÚ! P INT_IRQ4_SRC_GP0_INT_Msk ðÚ! P INT_IRQ4_SRC_GP1_INT_Pos èÚ! P INT_IRQ4_SRC_GP1_INT_Msk ïÚ! P INT_IRQ5_SRC_GP2_INT_Pos æÚ! P INT_IRQ5_SRC_GP2_INT_Msk íÚ! P INT_IRQ5_SRC_GP3_INT_Pos åÚ! P INT_IRQ5_SRC_GP3_INT_Msk ìÚ! P INT_IRQ5_SRC_GP4_INT_Pos äÚ! P INT_IRQ5_SRC_GP4_INT_Msk ëÚ! P INT_IRQ6_SRC_PWM_INT_Pos ºÚ! P INT_IRQ6_SRC_PWM_INT_Msk ÁÚ# P INT_IRQ7_SRC_BRAKE_INT_Pos DÚ# P INT_IRQ7_SRC_BRAKE_INT_Msk KÚ" P INT_IRQ8_SRC_TMR0_INT_Pos ‡Ú" P INT_IRQ8_SRC_TMR0_INT_Msk ŽÚ" P INT_IRQ9_SRC_TMR1_INT_Pos …Ú" P INT_IRQ9_SRC_TMR1_INT_Msk ŒÚ$ P INT_IRQ12_SRC_UART0_INT_Pos Ú$ P INT_IRQ12_SRC_UART0_INT_Msk Ú$ P INT_IRQ13_SRC_UART1_INT_Pos
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Ú$ P INT_IRQ13_SRC_UART1_INT_Msk Ú" P INT_IRQ14_SRC_SPI_INT_Pos ‘Ú" P INT_IRQ14_SRC_SPI_INT_Msk ˜Ú" P INT_IRQ16_SRC_GP5_INT_Pos ¯Ú" P INT_IRQ16_SRC_GP5_INT_Msk ¶Ú( P INT_IRQ17_SRC_HIRC_TRIM_INT_Pos Ú( P INT_IRQ17_SRC_HIRC_TRIM_INT_Msk ´Ú# P INT_IRQ18_SRC_I2C0_INT_Pos ‰Ú# P INT_IRQ18_SRC_I2C0_INT_Msk �Ú# P INT_IRQ19_SRC_I2C1_INT_Pos ‡Ú# P INT_IRQ19_SRC_I2C1_INT_Msk ŽÚ# P INT_IRQ25_SRC_ACMP_INT_Pos XÚ# P INT_IRQ25_SRC_ACMP_INT_Msk _Ú$ P INT_IRQ28_SRC_PWRWU_INT_Pos ÏÚ$ P INT_IRQ28_SRC_PWRWU_INT_Msk ÖÚ" P INT_IRQ29_SRC_ADC_INT_Pos ¯Ú" P INT_IRQ29_SRC_ADC_INT_Msk ¶Ú P INT_CON_NMI_SEL_Pos dÚ P INT_CON_NMI_SEL_Msk kÚ P INT_CON_NMI_SEL_EN_Pos lÚ P INT_CON_NMI_SEL_EN_Msk sÚ P INT_IRQ_MCU_IRQ_Pos OÚ P INT_IRQ_MCU_IRQ_Msk VÚ 8
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<unnamed> QÚ
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" ¾CLKPSC 7Ú
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" ¾CLKDIV :Ú
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" ¾CTL Ú
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" ¾PERIOD0 Ú
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" ¾PERIOD1 Ú
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" ¾PERIOD2 Ú
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" ¾PERIOD3 ÿÚ
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" ¾PERIOD4 þÚ
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" ¾PERIOD5 ýÚ
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" ¾CMPDAT0 Ú
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" ¾CMPDAT1 Ú
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" ¾CMPDAT2
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Ú
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" ¾CMPDAT3 Ú
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" ¾CMPDAT4 Ú
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" ¾CMPDAT5 Ú <" ¾
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RESERVED0 Ú
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" ¾INTEN {Ú
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" ¾INTSTS Ú
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" ¾POEN ÉÚ
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" ¾BRKCTL 5Ú
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" ¾DTCTL ~Ú
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" ¾ ADCTCTL0 ÄÚ
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" ¾ ADCTCTL1 ÃÚ
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" ¾ ADCTSTS0 Ú
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" ¾ ADCTSTS1 ¬Ú
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" ¾PHCHG �Ú
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" ¾ PHCHGNXT �Ú
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" ¾ PHCHGMSK žÚ
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" ¾IFA -Ú
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" ¾PCACTL @Ú
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" ¾ MSKALIGN �Ú PWM_T PÚ P PWM_CLKPSC_CLKPSC01_Pos yÚ P PWM_CLKPSC_CLKPSC01_Msk €Ú P PWM_CLKPSC_CLKPSC23_Pos uÚ P PWM_CLKPSC_CLKPSC23_Msk |Ú P PWM_CLKPSC_CLKPSC45_Pos qÚ P PWM_CLKPSC_CLKPSC45_Msk xÚ P PWM_CLKDIV_CLKDIV0_Pos ²Ú P PWM_CLKDIV_CLKDIV0_Msk ¹Ú P PWM_CLKDIV_CLKDIV1_Pos ±Ú P PWM_CLKDIV_CLKDIV1_Msk ¸Ú P PWM_CLKDIV_CLKDIV2_Pos °Ú P PWM_CLKDIV_CLKDIV2_Msk ·Ú P PWM_CLKDIV_CLKDIV3_Pos ¯Ú P PWM_CLKDIV_CLKDIV3_Msk ¶Ú P PWM_CLKDIV_CLKDIV4_Pos ®Ú P PWM_CLKDIV_CLKDIV4_Msk µÚ P PWM_CLKDIV_CLKDIV5_Pos Ú P PWM_CLKDIV_CLKDIV5_Msk ´Ú P PWM_CTL_CNTEN0_Pos ÙÚ P PWM_CTL_CNTEN0_Msk àÚ P PWM_CTL_DBGTRIOFF_Pos äÚ P PWM_CTL_DBGTRIOFF_Msk ëÚ P PWM_CTL_PINV0_Pos Ú P PWM_CTL_PINV0_Msk Ú P PWM_CTL_CNTMODE0_Pos CÚ P PWM_CTL_CNTMODE0_Msk JÚ P PWM_CTL_CNTEN1_Pos ØÚ P PWM_CTL_CNTEN1_Msk ßÚ P PWM_CTL_HCUPDT_Pos ¹Ú P PWM_CTL_HCUPDT_Msk ÀÚ P PWM_CTL_PINV1_Pos Ú P PWM_CTL_PINV1_Msk Ú P PWM_CTL_CNTMODE1_Pos BÚ P PWM_CTL_CNTMODE1_Msk IÚ P PWM_CTL_CNTEN2_Pos ×Ú P PWM_CTL_CNTEN2_Msk ÞÚ P PWM_CTL_PINV2_Pos Ú P PWM_CTL_PINV2_Msk Ú P PWM_CTL_CNTMODE2_Pos AÚ P PWM_CTL_CNTMODE2_Msk HÚ P PWM_CTL_CNTEN3_Pos ÖÚ P PWM_CTL_CNTEN3_Msk ÝÚ P PWM_CTL_PINV3_Pos Ú P PWM_CTL_PINV3_Msk Ú P PWM_CTL_CNTMODE3_Pos @Ú P PWM_CTL_CNTMODE3_Msk GÚ P PWM_CTL_CNTEN4_Pos ÕÚ P PWM_CTL_CNTEN4_Msk ÜÚ P PWM_CTL_PINV4_Pos Ú P PWM_CTL_PINV4_Msk Ú P PWM_CTL_CNTMODE4_Pos ?Ú P PWM_CTL_CNTMODE4_Msk FÚ P PWM_CTL_CNTEN5_Pos ÔÚ P PWM_CTL_CNTEN5_Msk ÛÚ P PWM_CTL_ASYMEN_Pos ´Ú P PWM_CTL_ASYMEN_Msk »Ú P PWM_CTL_PINV5_Pos Ú P PWM_CTL_PINV5_Msk Ú P PWM_CTL_CNTMODE5_Pos >Ú P PWM_CTL_CNTMODE5_Msk EÚ P PWM_CTL_DTCNT01_Pos ¡Ú P PWM_CTL_DTCNT01_Msk ¨Ú P PWM_CTL_DTCNT23_Pos �Ú P PWM_CTL_DTCNT23_Msk ¤Ú P PWM_CTL_DTCNT45_Pos ™Ú P PWM_CTL_DTCNT45_Msk Ú P PWM_CTL_CNTCLR_Pos »Ú P PWM_CTL_CNTCLR_Msk ÂÚ P PWM_CTL_MODE_Pos `Ú P PWM_CTL_MODE_Msk gÚ P PWM_CTL_GROUPEN_Pos _Ú P PWM_CTL_GROUPEN_Msk fÚ P PWM_CTL_CNTTYPE_Pos XÚ P PWM_CTL_CNTTYPE_Msk _Ú P PWM_PERIOD0_PERIOD0_Pos tÚ P PWM_PERIOD0_PERIOD0_Msk {Ú P PWM_PERIOD0_PERIOD1_Pos sÚ P PWM_PERIOD0_PERIOD1_Msk zÚ P PWM_PERIOD0_PERIOD2_Pos rÚ P PWM_PERIOD0_PERIOD2_Msk yÚ P PWM_PERIOD0_PERIOD3_Pos qÚ P PWM_PERIOD0_PERIOD3_Msk xÚ P PWM_PERIOD0_PERIOD4_Pos pÚ P PWM_PERIOD0_PERIOD4_Msk wÚ P PWM_PERIOD0_PERIOD5_Pos oÚ P PWM_PERIOD0_PERIOD5_Msk vÚ P PWM_PERIOD1_PERIOD0_Pos sÚ P PWM_PERIOD1_PERIOD0_Msk zÚ P PWM_PERIOD1_PERIOD1_Pos rÚ P PWM_PERIOD1_PERIOD1_Msk yÚ P PWM_PERIOD1_PERIOD2_Pos qÚ P PWM_PERIOD1_PERIOD2_Msk xÚ P PWM_PERIOD1_PERIOD3_Pos pÚ P PWM_PERIOD1_PERIOD3_Msk wÚ P PWM_PERIOD1_PERIOD4_Pos oÚ P PWM_PERIOD1_PERIOD4_Msk vÚ P PWM_PERIOD1_PERIOD5_Pos nÚ P PWM_PERIOD1_PERIOD5_Msk uÚ P PWM_PERIOD2_PERIOD0_Pos rÚ P PWM_PERIOD2_PERIOD0_Msk yÚ P PWM_PERIOD2_PERIOD1_Pos qÚ P PWM_PERIOD2_PERIOD1_Msk xÚ P PWM_PERIOD2_PERIOD2_Pos pÚ P PWM_PERIOD2_PERIOD2_Msk wÚ P PWM_PERIOD2_PERIOD3_Pos oÚ P PWM_PERIOD2_PERIOD3_Msk vÚ P PWM_PERIOD2_PERIOD4_Pos nÚ P PWM_PERIOD2_PERIOD4_Msk uÚ P PWM_PERIOD2_PERIOD5_Pos mÚ P PWM_PERIOD2_PERIOD5_Msk tÚ P PWM_PERIOD3_PERIOD0_Pos qÚ P PWM_PERIOD3_PERIOD0_Msk xÚ P PWM_PERIOD3_PERIOD1_Pos pÚ P PWM_PERIOD3_PERIOD1_Msk wÚ P PWM_PERIOD3_PERIOD2_Pos oÚ P PWM_PERIOD3_PERIOD2_Msk vÚ P PWM_PERIOD3_PERIOD3_Pos nÚ P PWM_PERIOD3_PERIOD3_Msk uÚ P PWM_PERIOD3_PERIOD4_Pos mÚ P PWM_PERIOD3_PERIOD4_Msk tÚ P PWM_PERIOD3_PERIOD5_Pos lÚ P PWM_PERIOD3_PERIOD5_Msk sÚ P PWM_PERIOD4_PERIOD0_Pos pÚ P PWM_PERIOD4_PE
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Ú! P PWM_ADCTSTS0_CUTRGF3_Pos Ú! P PWM_ADCTSTS0_CUTRGF3_Msk Ú! P PWM_ADCTSTS0_CPTRGF3_Pos Ú! P PWM_ADCTSTS0_CPTRGF3_Msk Ú! P PWM_ADCTSTS0_CDTRGF3_Pos %Ú! P PWM_ADCTSTS0_CDTRGF3_Msk ,Ú! P PWM_ADCTSTS0_ZPTRGF3_Pos Ú! P PWM_ADCTSTS0_ZPTRGF3_Msk Ú! P PWM_ADCTSTS1_CUTRGF4_Pos Ú! P PWM_ADCTSTS1_CUTRGF4_Msk Ú! P PWM_ADCTSTS1_CPTRGF4_Pos Ú! P PWM_ADCTSTS1_CPTRGF4_Msk Ú! P PWM_ADCTSTS1_CDTRGF4_Pos #Ú! P PWM_ADCTSTS1_CDTRGF4_Msk *Ú! P PWM_ADCTSTS1_ZPTRGF4_Pos Ú! P PWM_ADCTSTS1_ZPTRGF4_Msk Ú! P PWM_ADCTSTS1_CUTRGF5_Pos Ú! P PWM_ADCTSTS1_CUTRGF5_Msk Ú! P PWM_ADCTSTS1_CPTRGF5_Pos Ú! P PWM_ADCTSTS1_CPTRGF5_Msk Ú! P PWM_ADCTSTS1_CDTRGF5_Pos "Ú! P PWM_ADCTSTS1_CDTRGF5_Msk )Ú! P PWM_ADCTSTS1_ZPTRGF5_Pos ÿÚ! P PWM_ADCTSTS1_ZPTRGF5_Msk Ú P PWM_PHCHG_MSKDAT0_Pos Ú P PWM_PHCHG_MSKDAT0_Msk Ú P PWM_PHCHG_MSKDAT1_Pos ÿÚ P PWM_PHCHG_MSKDAT1_Msk Ú P PWM_PHCHG_MSKDAT2_Pos þÚ P PWM_PHCHG_MSKDAT2_Msk Ú P PWM_PHCHG_MSKDAT3_Pos ýÚ P PWM_PHCHG_MSKDAT3_Msk Ú P PWM_PHCHG_MSKDAT4_Pos üÚ P PWM_PHCHG_MSKDAT4_Msk Ú P PWM_PHCHG_MSKDAT5_Pos ûÚ P PWM_PHCHG_MSKDAT5_Msk Ú P PWM_PHCHG_MSKDAT6_Pos úÚ P PWM_PHCHG_MSKDAT6_Msk Ú P PWM_PHCHG_MSKDAT7_Pos ùÚ P PWM_PHCHG_MSKDAT7_Msk Ú P PWM_PHCHG_MSKEN0_Pos HÚ P PWM_PHCHG_MSKEN0_Msk OÚ P PWM_PHCHG_MSKEN1_Pos GÚ P PWM_PHCHG_MSKEN1_Msk NÚ P PWM_PHCHG_MSKEN2_Pos FÚ P PWM_PHCHG_MSKEN2_Msk MÚ P PWM_PHCHG_MSKEN3_Pos EÚ P PWM_PHCHG_MSKEN3_Msk LÚ P PWM_PHCHG_MSKEN4_Pos DÚ P PWM_PHCHG_MSKEN4_Msk KÚ P PWM_PHCHG_MSKEN5_Pos CÚ P PWM_PHCHG_MSKEN5_Msk JÚ P PWM_PHCHG_AUTOCLR0_Pos ¨Ú P PWM_PHCHG_AUTOCLR0_Msk ¯Ú P PWM_PHCHG_AUTOCLR1_Pos §Ú P PWM_PHCHG_AUTOCLR1_Msk ®Ú P PWM_PHCHG_AOFFEN01_Pos âÚ P PWM_PHCHG_AOFFEN01_Msk éÚ P PWM_PHCHG_AOFFEN11_Pos áÚ P PWM_PHCHG_AOFFEN11_Msk èÚ P PWM_PHCHG_AOFFEN21_Pos àÚ P PWM_PHCHG_AOFFEN21_Msk çÚ P PWM_PHCHG_AOFFEN31_Pos ßÚ P PWM_PHCHG_AOFFEN31_Msk æÚ P PWM_PHCHG_A1POSSEL_Pos ªÚ P PWM_PHCHG_A1POSSEL_Msk ±Ú P PWM_PHCHG_TMR1TEN_Pos éÚ P PWM_PHCHG_TMR1TEN_Msk ðÚ P PWM_PHCHG_ACMP1TEN_Pos ¹Ú P PWM_PHCHG_ACMP1TEN_Msk ÀÚ P PWM_PHCHG_AOFFEN00_Pos ãÚ P PWM_PHCHG_AOFFEN00_Msk êÚ P PWM_PHCHG_AOFFEN10_Pos âÚ P PWM_PHCHG_AOFFEN10_Msk éÚ P PWM_PHCHG_AOFFEN20_Pos áÚ P PWM_PHCHG_AOFFEN20_Msk èÚ P PWM_PHCHG_AOFFEN30_Pos àÚ P PWM_PHCHG_AOFFEN30_Msk çÚ P PWM_PHCHG_A0POSSEL_Pos «Ú P PWM_PHCHG_A0POSSEL_Msk ²Ú P PWM_PHCHG_TMR0TEN_Pos êÚ P PWM_PHCHG_TMR0TEN_Msk ñÚ P PWM_PHCHG_ACMP0TEN_Pos ºÚ P PWM_PHCHG_ACMP0TEN_Msk ÁÚ! P PWM_PHCHGNXT_MSKDAT0_Pos Ú! P PWM_PHCHGNXT_MSKDAT0_Msk Ú! P PWM_PHCHGNXT_MSKDAT1_Pos ÿÚ! P PWM_PHCHGNXT_MSKDAT1_Msk Ú! P PWM_PHCHGNXT_MSKDAT2_Pos þÚ! P PWM_PHCHGNXT_MSKDAT2_Msk Ú! P PWM_PHCHGNXT_MSKDAT3_Pos ýÚ! P PWM_PHCHGNXT_MSKDAT3_Msk Ú! P PWM_PHCHGNXT_MSKDAT4_Pos üÚ! P PWM_PHCHGNXT_MSKDAT4_Msk Ú! P PWM_PHCHGNXT_MSKDAT5_Pos ûÚ! P PWM_PHCHGNXT_MSKDAT5_Msk Ú! P PWM_PHCHGNXT_MSKDAT6_Pos úÚ! P PWM_PHCHGNXT_MSKDAT6_Msk Ú! P PWM_PHCHGNXT_MSKDAT7_Pos ùÚ! P PWM_PHCHGNXT_MSKDAT7_Msk Ú P PWM_PHCHGNXT_MSKEN0_Pos HÚ P PWM_PHCHGNXT_MSKEN0_Msk OÚ P PWM_PHCHGNXT_MSKEN1_Pos GÚ P PWM_PHCHGNXT_MSKEN1_Msk NÚ P PWM_PHCHGNXT_MSKEN2_Pos FÚ P PWM_PHCHGNXT_MSKEN2_Msk MÚ P PWM_PHCHGNXT_MSKEN3_Pos EÚ P PWM_PHCHGNXT_MSKEN3_Msk LÚ P PWM_PHCHGNXT_MSKEN4_Pos DÚ P PWM_PHCHGNXT_MSKEN4_Msk KÚ P PWM_PHCHGNXT_MSKEN5_Pos CÚ P PWM_PHCHGNXT_MSKEN5_Msk JÚ" P PWM_PHCHGNXT_AUTOCLR0_Pos ¨Ú" P PWM_PHCHGNXT_AUTOCLR0_Msk ¯Ú" P PWM_PHCHGNXT_AUTOCLR1_Pos §Ú" P PWM_PHCHGNXT_AUTOCLR1_Msk ®Ú" P PWM_PHCHGNXT_AOFFEN01_Pos âÚ" P PWM_PHCHGNXT_AOFFEN01_Msk éÚ" P PWM_PHC
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Ú! P PWM_MSKALIGN_MSKDAT4_Msk Ú! P PWM_MSKALIGN_MSKDAT5_Pos Ú! P PWM_MSKALIGN_MSKDAT5_Msk Ú P PWM_MSKALIGN_MSKEN0_Pos VÚ P PWM_MSKALIGN_MSKEN0_Msk ]Ú P PWM_MSKALIGN_MSKEN1_Pos UÚ P PWM_MSKALIGN_MSKEN1_Msk \Ú P PWM_MSKALIGN_MSKEN2_Pos TÚ P PWM_MSKALIGN_MSKEN2_Msk [Ú P PWM_MSKALIGN_MSKEN3_Pos SÚ P PWM_MSKALIGN_MSKEN3_Msk ZÚ P PWM_MSKALIGN_MSKEN4_Pos RÚ P PWM_MSKALIGN_MSKEN4_Msk YÚ P PWM_MSKALIGN_MSKEN5_Pos QÚ P PWM_MSKALIGN_MSKEN5_Msk XÚ P PWM_MSKALIGN_ALIGN0_Pos iÚ P PWM_MSKALIGN_ALIGN0_Msk pÚ P PWM_MSKALIGN_ALIGN1_Pos hÚ P PWM_MSKALIGN_ALIGN1_Msk oÚ P PWM_MSKALIGN_ALIGN2_Pos gÚ P PWM_MSKALIGN_ALIGN2_Msk nÚ P PWM_MSKALIGN_ALIGN3_Pos fÚ P PWM_MSKALIGN_ALIGN3_Msk mÚ P PWM_MSKALIGN_ALIGN4_Pos eÚ P PWM_MSKALIGN_ALIGN4_Msk lÚ P PWM_MSKALIGN_ALIGN5_Pos dÚ P PWM_MSKALIGN_ALIGN5_Msk kÚ 8
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<unnamed> QÚ
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" £CTL /Ú
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" £CLKDIV OÚ
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" £SSCTL …Ú <" £
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RESERVED0 DÚ
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" £RX jÚ <" £
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RESERVED1 ;Ú
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" £TX hÚ <" £
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RESERVED2 .Ú
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" £SLVCTL 4Ú
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" £FIFOCTL Ú
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" £STATUS (Ú SPI_T XÚ P SPI_CTL_SPIEN_Pos Ú P SPI_CTL_SPIEN_Msk Ú P SPI_CTL_RXNEG_Pos Ú P SPI_CTL_RXNEG_Msk Ú P SPI_CTL_TXNEG_Pos Ú P SPI_CTL_TXNEG_Msk Ú P SPI_CTL_DWIDTH_Pos ÅÚ P SPI_CTL_DWIDTH_Msk ÌÚ P SPI_CTL_LSB_Pos ®Ú P SPI_CTL_LSB_Msk µÚ P SPI_CTL_CLKPOL_Pos ÄÚ P SPI_CTL_CLKPOL_Msk ËÚ P SPI_CTL_SUSPITV_Pos IÚ P SPI_CTL_SUSPITV_Msk PÚ P SPI_CTL_UNITIF_Pos ºÚ P SPI_CTL_UNITIF_Msk ÁÚ P SPI_CTL_UNITIEN_Pos kÚ P SPI_CTL_UNITIEN_Msk rÚ P SPI_CTL_SLAVE_Pos Ú P SPI_CTL_SLAVE_Msk Ú P SPI_CTL_REORDER_Pos tÚ P SPI_CTL_REORDER_Msk {Ú P SPI_CTL_FIFOEN_Pos ÒÚ P SPI_CTL_FIFOEN_Msk ÙÚ P SPI_CTL_RXEMPTY_Pos NÚ P SPI_CTL_RXEMPTY_Msk UÚ P SPI_CTL_RXFULL_Pos ¬Ú P SPI_CTL_RXFULL_Msk ³Ú P SPI_CTL_TXEMPTY_Pos LÚ P SPI_CTL_TXEMPTY_Msk SÚ P SPI_CTL_TXFULL_Pos ªÚ P SPI_CTL_TXFULL_Msk ±Ú P SPI_CLKDIV_DIVIDER_Pos Ú P SPI_CLKDIV_DIVIDER_Msk §Ú P SPI_SSCTL_SS_Pos AÚ P SPI_SSCTL_SS_Msk HÚ P SPI_SSCTL_SSACTPOL_Pos rÚ P SPI_SSCTL_SSACTPOL_Msk yÚ P SPI_SSCTL_AUTOSS_Pos Ú P SPI_SSCTL_AUTOSS_Msk Ú P SPI_SSCTL_SSLTEN_Pos Ú P SPI_SSCTL_SSLTEN_Msk
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Ú P SPI_SSCTL_LTF_Pos ÿÚ P SPI_SSCTL_LTF_Msk Ú P SPI_RX_RX_Pos "Ú P SPI_RX_RX_Msk )Ú P SPI_TX_TX_Pos Ú P SPI_TX_TX_Msk %Ú P SPI_SLVCTL_SLV3WIRE_Pos +Ú P SPI_SLVCTL_SLV3WIRE_Msk 2Ú P SPI_SLVCTL_SLVABT_Pos ÂÚ P SPI_SLVCTL_SLVABT_Msk ÉÚ P SPI_SLVCTL_SLVSTIEN_Pos Ú P SPI_SLVCTL_SLVSTIEN_Msk Ú P SPI_SLVCTL_SLVSTIF_Pos aÚ P SPI_SLVCTL_SLVSTIF_Msk hÚ P SPI_SLVCTL_SSINAIEN_Pos 0Ú P SPI_SLVCTL_SSINAIEN_Msk 7Ú P SPI_SLVCTL_DIVMOD_Pos ËÚ P SPI_SLVCTL_DIVMOD_Msk ÒÚ P SPI_FIFOCTL_RXRST_Pos ¼Ú P SPI_FIFOCTL_RXRST_Msk ÃÚ P SPI_FIFOCTL_TXRST_Pos ºÚ P SPI_FIFOCTL_TXRST_Msk ÁÚ P SPI_FIFOCTL_RXTHIEN_Pos 9Ú P SPI_FIFOCTL_RXTHIEN_Msk @Ú P SPI_FIFOCTL_TXTHIEN_Pos 7Ú P SPI_FIFOCTL_TXTHIEN_Msk >Ú P SPI_FIFOCTL_RXOVIEN_Pos 0Ú P SPI_FIFOCTL_RXOVIEN_Msk 7Ú P SPI_FIFOCTL_RXTOIEN_Pos 2Ú P SPI_FIFOCTL_RXTOIEN_Msk 9Ú P SPI_FIFOCTL_RXTH_Pos Ú P SPI_FIFOCTL_RXTH_Msk "Ú P SPI_FIFOCTL_TXTH_Pos Ú P SPI_FIFOCTL_TXTH_Msk Ú P SPI_STATUS_RXTHIF_Pos Ú P SPI_STATUS_RXTHIF_Msk ´Ú P SPI_STATUS_RXOVIF_Pos ¤Ú P SPI_STATUS_RXOVIF_Msk «Ú P SPI_STATUS_TXTHIF_Pos «Ú P SPI_STATUS_TXTHIF_Msk ²Ú P SPI_STATUS_SLVSTIF_Pos UÚ P SPI_STATUS_SLVSTIF_Msk \Ú P SPI_STATUS_RXCNT_Pos õÚ P SPI_STATUS_RXCNT_Msk üÚ P SPI_STATUS_UNITIF_Pos ³Ú P SPI_STATUS_UNITIF_Msk ºÚ P SPI_STATUS_SLVTOIF_Pos YÚ P SPI_STATUS_SLVTOIF_Msk `Ú P SPI_STATUS_RXEMPTY_Pos GÚ P SPI_STATUS_RXEMPTY_Msk NÚ P SPI_STATUS_RXFULL_Pos ¥Ú P SPI_STATUS_RXFULL_Msk ¬Ú P SPI_STATUS_TXEMPTY_Pos EÚ P SPI_STATUS_TXEMPTY_Msk LÚ P SPI_STATUS_TXFULL_Pos £Ú P SPI_STATUS_TXFULL_Msk ªÚ P SPI_STATUS_TXCNT_Pos óÚ P SPI_STATUS_TXCNT_Msk úÚ 8
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<unnamed> QÚ
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" ”PDID ýÚ
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" ”RSTSTS 'Ú
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" ”IPRST0 XÚ
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" ”IPRST1 WÚ <" ”
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RESERVED0 NÚ
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" ”BODCTL bÚ <" ”
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RESERVED1 AÚ
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" ”P0_MFP XÚ
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" ”P1_MFP WÚ
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" ”P2_MFP VÚ
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" ”P3_MFP UÚ
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" ”P4_MFP TÚ
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" ”P5_MFP SÚ <" 8”
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RESERVED2 Ú
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" ”IRCTCTL Ú
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" ”IRCTIEN
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Ú
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" ” IRCTISTS ¡Ú <" t”
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RESERVED3 ßÚ
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" ”REGLCTL Ú SYS_T EÚ P SYS_PDID_PDID_Pos Ú P SYS_PDID_PDID_Msk Ú P SYS_RSTSTS_PORF_Pos -Ú P SYS_RSTSTS_PORF_Msk 4Ú P SYS_RSTSTS_PINRF_Pos ãÚ P SYS_RSTSTS_PINRF_Msk êÚ P SYS_RSTSTS_WDTRF_Pos ÛÚ P SYS_RSTSTS_WDTRF_Msk âÚ P SYS_RSTSTS_BODRF_Pos õÚ P SYS_RSTSTS_BODRF_Msk üÚ P SYS_RSTSTS_SYSRF_Pos ËÚ P SYS_RSTSTS_SYSRF_Msk ÒÚ P SYS_RSTSTS_CPURF_Pos âÚ P SYS_RSTSTS_CPURF_Msk éÚ P SYS_RSTSTS_CPULKRF_Pos GÚ P SYS_RSTSTS_CPULKRF_Msk NÚ P SYS_IPRST0_CHIPRST_Pos rÚ P SYS_IPRST0_CHIPRST_Msk yÚ P SYS_IPRST0_CPURST_Pos °Ú P SYS_IPRST0_CPURST_Msk ·Ú P SYS_IPRST1_GPIORST_Pos fÚ P SYS_IPRST1_GPIORST_Msk mÚ P SYS_IPRST1_TMR0RST_Pos rÚ P SYS_IPRST1_TMR0RST_Msk yÚ P SYS_IPRST1_TMR1RST_Pos qÚ P SYS_IPRST1_TMR1RST_Msk xÚ P SYS_IPRST1_I2C0RST_Pos §Ú P SYS_IPRST1_I2C0RST_Msk ®Ú P SYS_IPRST1_I2C1RST_Pos ¦Ú P SYS_IPRST1_I2C1RST_Msk Ú P SYS_IPRST1_SPI0RST_Pos yÚ P SYS_IPRST1_SPI0RST_Msk €Ú P SYS_IPRST1_UART0RST_Pos 'Ú P SYS_IPRST1_UART0RST_Msk .Ú P SYS_IPRST1_UART1RST_Pos &Ú P SYS_IPRST1_UART1RST_Msk -Ú P SYS_IPRST1_PWM0RST_Pos qÚ P SYS_IPRST1_PWM0RST_Msk xÚ P SYS_IPRST1_ACMPRST_Pos tÚ P SYS_IPRST1_ACMPRST_Msk {Ú P SYS_IPRST1_ADCRST_Pos ÏÚ P SYS_IPRST1_ADCRST_Msk ÖÚ P SYS_BODCTL_BODEN_Pos 5Ú P SYS_BODCTL_BODEN_Msk <Ú P SYS_BODCTL_BODVL_Pos &Ú P SYS_BODCTL_BODVL_Msk -Ú P SYS_BODCTL_BODRSTEN_Pos 6Ú P SYS_BODCTL_BODRSTEN_Msk =Ú P SYS_BODCTL_BODIF_Pos 9Ú P SYS_BODCTL_BODIF_Msk @Ú P SYS_BODCTL_BODLPM_Pos ÝÚ P SYS_BODCTL_BODLPM_Msk äÚ P SYS_BODCTL_BODOUT_Pos ÎÚ P SYS_BODCTL_BODOUT_Msk ÕÚ P SYS_P0_MFP_MFP_Pos ´Ú P SYS_P0_MFP_MFP_Msk »Ú P SYS_P0_MFP_ALT0_Pos „Ú P SYS_P0_MFP_ALT0_Msk ‹Ú P SYS_P0_MFP_ALT1_Pos ƒÚ P SYS_P0_MFP_ALT1_Msk ŠÚ P SYS_P0_MFP_ALT4_Pos €Ú P SYS_P0_MFP_ALT4_Msk ‡Ú P SYS_P0_MFP_ALT5_Pos Ú P SYS_P0_MFP_ALT5_Msk †Ú P SYS_P0_MFP_ALT6_Pos ~Ú P SYS_P0_MFP_ALT6_Msk …Ú P SYS_P0_MFP_ALT7_Pos }Ú P SYS_P0_MFP_ALT7_Msk „Ú P SYS_P0_MFP_TYPE_Pos SÚ P SYS_P0_MFP_TYPE_Msk ZÚ P SYS_P1_MFP_MFP_Pos ³Ú P SYS_P1_MFP_MFP_Msk ºÚ P SYS_P1_MFP_ALT0_Pos ƒÚ P SYS_P1_MFP_ALT0_Msk ŠÚ P SYS_P1_MFP_ALT2_Pos �Ú P SYS_P1_MFP_ALT2_Msk ˆÚ P SYS_P1_MFP_ALT3_Pos €Ú P SYS_P1_MFP_ALT3_Msk ‡Ú P SYS_P1_MFP_ALT4_Pos Ú P SYS_P1_MFP_ALT4_Msk †Ú P SYS_P1_MFP_ALT5_Pos ~Ú P SYS_P1_MFP_ALT5_Msk …Ú P SYS_P1_MFP_TYPE_Pos RÚ P SYS_P1_MFP_TYPE_Msk YÚ P SYS_P1_MFP_P12EXT_Pos ìÚ P SYS_P1_MFP_P12EXT_Msk óÚ P SYS_P1_MFP_P13EXT_Pos ëÚ P SYS_P1_MFP_P13EXT_Msk òÚ P SYS_P1_MFP_P14EXT_Pos êÚ P SYS_P1_MFP_P14EXT_Msk ñÚ P SYS_P2_MFP_MFP_Pos ²Ú P SYS_P2_MFP_MFP_Msk ¹Ú P SYS_P2_MFP_ALT2_Pos €Ú P SYS_P2_MFP_ALT2_Msk ‡Ú P SYS_P2_MFP_ALT3_Pos Ú P SYS_P2_MFP_ALT3_Msk †Ú P SYS_P2_MFP_ALT4_Pos ~Ú P SYS_P2_MFP_ALT4_Msk …Ú P SYS_P2_MFP_ALT5_Pos }Ú P SYS_P2_MFP_ALT5_Msk „Ú P SYS_P2_MFP_ALT6_Pos |Ú P SYS_P2_MFP_ALT6_Msk ƒÚ P SYS_P2_MFP_TYPE_Pos QÚ P SYS_P2_MFP_TYPE_Msk XÚ P SYS_P3_MFP_MFP_Pos ±Ú P SYS_P3_MFP_MFP_Msk ¸Ú P SYS_P3_MFP_ALT0_Pos �Ú P SYS_P3_MFP_ALT0_Msk ˆÚ P SYS_P3_MFP_ALT1_Pos €Ú P SYS_P3_MFP_ALT1_Msk ‡Ú P SYS_P3_MFP_ALT2_Pos Ú P SYS_P3_MFP_ALT2_Msk †Ú P SYS_P3_MFP_ALT4_Pos }Ú P SYS_P3_MFP_ALT4_Msk „Ú P SYS_P3_MFP_ALT5_Pos |Ú P SYS_P3_MFP_ALT5_Msk ƒÚ P SYS_P3_MFP_ALT6_Pos {Ú P SYS_P3_MFP_ALT6_Msk ‚Ú P SYS_P3_MFP_TYPE_Pos PÚ P SYS_P3_MFP_TYPE_Msk WÚ P SYS_P3_MFP_P32EXT_Pos èÚ P SYS_P3_MFP_P32EXT_Msk ïÚ P SYS_P4_MFP_MFP_Pos °Ú P SYS_P4_MFP_MFP_Msk ·Ú P SYS_P4_MFP_ALT6_Pos zÚ P SYS_P4_MFP_ALT6_Msk �Ú P SYS_P4_MFP_ALT7_Pos yÚ P
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<unnamed> QÚ
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" ËCTL Ú
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" ËCMP Ú
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" ËINTSTS ýÚ
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" ËCNT Ú
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" ËCAP Ú
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" ËEXTCTL Ú
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" ËEINTSTS ¶Ú TIMER_T ¿Ú P TIMER_CTL_PSC_Pos Ú P TIMER_CTL_PSC_Msk Ú P TIMER_CTL_CMPCTL_Pos -Ú P TIMER_CTL_CMPCTL_Msk 4Ú P TIMER_CTL_TGLPINSEL_Pos 8Ú P TIMER_CTL_TGLPINSEL_Msk ?Ú P TIMER_CTL_CAPSRC_Pos 4Ú P TIMER_CTL_CAPSRC_Msk ;Ú P TIMER_CTL_WKEN_Pos ¿Ú P TIMER_CTL_WKEN_Msk ÆÚ P TIMER_CTL_EXTCNTEN_Pos ƒÚ P TIMER_CTL_EXTCNTEN_Msk ŠÚ P TIMER_CTL_ACTSTS_Pos Ú P TIMER_CTL_ACTSTS_Msk %Ú P TIMER_CTL_RSTCNT_Pos Ú P TIMER_CTL_RSTCNT_Msk Ú P TIMER_CTL_OPMODE_Pos ,Ú P TIMER_CTL_OPMODE_Msk 3Ú P TIMER_CTL_INTEN_Pos tÚ P TIMER_CTL_INTEN_Msk {Ú P TIMER_CTL_CNTEN_Pos zÚ P TIMER_CTL_CNTEN_Msk �Ú P TIMER_CTL_ICEDEBUG_Pos ´Ú P TIMER_CTL_ICEDEBUG_Msk »Ú P TIMER_CMP_CMPDAT_Pos :Ú P TIMER_CMP_CMPDAT_Msk AÚ P TIMER_INTSTS_TIF_Pos Ú P TIMER_INTSTS_TIF_Msk Ú P TIMER_INTSTS_TWKF_Pos °Ú P TIMER_INTSTS_TWKF_Msk ·Ú P TIMER_CNT_CNT_Pos Ú P TIMER_CNT_CNT_Msk Ú P TIMER_CAP_CAPDAT_Pos RÚ P TIMER_CAP_CAPDAT_Msk YÚ" P TIMER_EXTCTL_CNTPHASE_Pos ŸÚ" P TIMER_EXTCTL_CNTPHASE_Msk ¦Ú! P TIMER_EXTCTL_CAPEDGE_Pos Ú! P TIMER_EXTCTL_CAPEDGE_Msk Ú P TIMER_EXTCTL_CAPEN_Pos ”Ú P TIMER_EXTCTL_CAPEN_Msk ›Ú" P TIMER_EXTCTL_CAPFUNCS_Pos ¢Ú" P TIMER_EXTCTL_CAPFUNCS_Msk ©Ú P TIMER_EXTCTL_CAPIEN_Pos IÚ P TIMER_EXTCTL_CAPIEN_Msk PÚ! P TIMER_EXTCTL_CAPDBEN_Pos
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Ú! P TIMER_EXTCTL_CAPDBEN_Msk Ú! P TIMER_EXTCTL_CNTDBEN_Pos ùÚ! P TIMER_EXTCTL_CNTDBEN_Msk Ú P TIMER_EXTCTL_CAPSEL_Pos AÚ P TIMER_EXTCTL_CAPSEL_Msk HÚ" P TIMER_EXTCTL_ACMPSSEL_Pos �Ú" P TIMER_EXTCTL_ACMPSSEL_Msk ¤Ú P TIMER_EINTSTS_CAPIF_Pos @Ú P TIMER_EINTSTS_CAPIF_Msk GÚ 8
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<unnamed> QÚ
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" ŠDAT OÚ
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" ŠINTEN ¦Ú
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" ŠFIFO Ú
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" ŠLINE þÚ
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" ŠMODEM ²Ú
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" Š MODEMSTS ²Ú
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" ŠFIFOSTS Ú
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" ŠINTSTS =Ú
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" ŠTOUT ÚÚ
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" ŠBAUD
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Ú
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" ŠIRDA Ú
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" ŠALTCTL ^Ú
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" ŠFUNSEL UÚ UART_T Ú P UART_DAT_DAT_Pos nÚ P UART_DAT_DAT_Msk uÚ P UART_INTEN_RDAIEN_Pos åÚ P UART_INTEN_RDAIEN_Msk ìÚ P UART_INTEN_THREIEN_Pos ‡Ú P UART_INTEN_THREIEN_Msk ŽÚ P UART_INTEN_RLSIEN_Pos ËÚ P UART_INTEN_RLSIEN_Msk ÒÚ P UART_INTEN_MODEMIEN_Pos FÚ P UART_INTEN_MODEMIEN_Msk MÚ P UART_INTEN_RXTOIEN_Pos mÚ P UART_INTEN_RXTOIEN_Msk tÚ! P UART_INTEN_BUFERRIEN_Pos ðÚ! P UART_INTEN_BUFERRIEN_Msk ÷Ú P UART_INTEN_WKCTSIEN_Pos ,Ú P UART_INTEN_WKCTSIEN_Msk 3Ú P UART_INTEN_TOCNTEN_Pos {Ú P UART_INTEN_TOCNTEN_Msk ‚Ú P UART_INTEN_ATORTSEN_Pos $Ú P UART_INTEN_ATORTSEN_Msk +Ú P UART_INTEN_ATOCTSEN_Pos 3Ú P UART_INTEN_ATOCTSEN_Msk :Ú P UART_FIFO_RXRST_Pos SÚ P UART_FIFO_RXRST_Msk ZÚ P UART_FIFO_TXRST_Pos QÚ P UART_FIFO_TXRST_Msk XÚ P UART_FIFO_RFITL_Pos uÚ P UART_FIFO_RFITL_Msk |Ú P UART_FIFO_RXOFF_Pos qÚ P UART_FIFO_RXOFF_Msk xÚ P UART_FIFO_RTSTRGLV_Pos hÚ P UART_FIFO_RTSTRGLV_Msk oÚ P UART_LINE_WLS_Pos Ú P UART_LINE_WLS_Msk Ú P UART_LINE_NSB_Pos Ú P UART_LINE_NSB_Msk Ú P UART_LINE_PBE_Pos Ú P UART_LINE_PBE_Msk &Ú P UART_LINE_EPE_Pos Ú P UART_LINE_EPE_Msk #Ú P UART_LINE_SPE_Pos Ú P UART_LINE_SPE_Msk Ú P UART_LINE_BCB_Pos /Ú P UART_LINE_BCB_Msk 6Ú P UART_MODEM_RTS_Pos ±Ú P UART_MODEM_RTS_Msk ¸Ú P UART_MODEM_RTSACTLV_Pos -Ú P UART_MODEM_RTSACTLV_Msk 4Ú P UART_MODEM_RTSSTS_Pos ±Ú P UART_MODEM_RTSSTS_Msk ¸Ú" P UART_MODEMSTS_CTSDETF_Pos •Ú" P UART_MODEMSTS_CTSDETF_Msk œÚ! P UART_MODEMSTS_CTSSTS_Pos ÀÚ! P UART_MODEMSTS_CTSSTS_Msk ÇÚ# P UART_MODEMSTS_CTSACTLV_Pos <Ú# P UART_MODEMSTS_CTSACTLV_Msk CÚ P UART_FIFOSTS_RXOVIF_Pos Ú P UART_FIFOSTS_RXOVIF_Msk Ú" P UART_FIFOSTS_ADDRDETF_Pos ²Ú" P UART_FIFOSTS_ADDRDETF_Msk ¹Ú P UART_FIFOSTS_PEF_Pos Ú P UART_FIFOSTS_PEF_Msk &Ú P UART_FIFOSTS_FEF_Pos )Ú P UART_FIFOSTS_FEF_Msk 0Ú P UART_FIFOSTS_BIF_Pos )Ú P UART_FIFOSTS_BIF_Msk 0Ú P UART_FIFOSTS_RXPTR_Pos VÚ P UART_FIFOSTS_RXPTR_Msk ]Ú! P UART_FIFOSTS_RXEMPTY_Pos ¹Ú! P UART_FIFOSTS_RXEMPTY_Msk ÀÚ P UART_FIFOSTS_RXFULL_Pos Ú P UART_FIFOSTS_RXFULL_Msk Ú P UART_FIFOSTS_TXPTR_Pos TÚ P UART_FIFOSTS_TXPTR_Msk [Ú! P UART_FIFOSTS_TXEMPTY_Pos ·Ú! P UART_FIFOSTS_TXEMPTY_Msk ¾Ú P UART_FIFOSTS_TXFULL_Pos Ú P UART_FIFOSTS_TXFULL_Msk Ú P UART_FIFOSTS_TXOVIF_Pos Ú P UART_FIFOSTS_TXOVIF_Msk Ú" P UART_FIFOSTS_TXEMPTYF_Pos oÚ" P UART_FIFOSTS_TXEMPTYF_Msk vÚ P UART_INTSTS_RDAIF_Pos ËÚ P UART_INTSTS_RDAIF_Msk ÒÚ P UART_INTSTS_THREIF_Pos mÚ P UART_INTSTS_THREIF_Msk tÚ P UART_INTSTS_RLSIF_Pos ±Ú P UART_INTSTS_RLSIF_Msk ¸Ú P UART_INTSTS_MODEMIF_Pos ,Ú P UART_INTSTS_MODEMIF_Msk 3Ú P UART_INTSTS_RXTOIF_Pos SÚ P UART_INTSTS_RXTOIF_Msk ZÚ! P UART_INTSTS_BUFERRIF_Pos ÖÚ! P UART_INTSTS_BUFERRIF_Msk ÝÚ P UART_INTSTS_RDAINT_Pos mÚ P UART_INTSTS_RDAINT_Msk tÚ P UART_INTSTS_THREINT_Pos Ú P UART_INTSTS_THREINT_Msk Ú P UART_INTSTS_RLSINT_Pos SÚ P UART_INTSTS_RLSINT_Msk ZÚ! P UART_INTSTS_MODEMINT_Pos ÎÚ! P UART_INTSTS_MODEMINT_Msk ÕÚ P UART_INTSTS_RXTOINT_Pos õÚ P UART_INTSTS_RXTOINT_Msk üÚ" P UART_INTSTS_BUFERRINT_Pos xÚ" P UART_INTSTS_BUFERRINT_Msk Ú P UART_INTSTS_CTSWKIF_Pos Ú P UART_INTSTS_CTSWKIF_Msk Ú P UART_TOUT_TOIC_Pos ¡Ú P UART_TOUT_TOIC_Msk ¨Ú P UART_TOUT_DLY_Pos éÚ P UART_TOUT_DLY_Msk ðÚ P UART_BAUD_BRD_Pos *Ú P UART_BAUD_BRD_Msk 1Ú P UART_BAUD_EDIVM1_Pos VÚ P UART_BAUD_EDIVM1_Msk ]Ú P UART_BAUD_BAUDM0_Pos cÚ P UART_BAUD_BAUDM0_Msk jÚ P UART_BAUD_BAUDM1_Pos bÚ P UART_BAUD_BAUDM1_Msk iÚ P UART_IRDA_TXEN_Pos ½Ú P UART_IRDA_TXEN_Msk ÄÚ P
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<unnamed> QÚ
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" £CTL +Ú
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" £ALTCTL DÚ WDT_T UÚ P WDT_CTL_RSTCNT_Pos ¨Ú P WDT_CTL_RSTCNT_Msk ¯Ú P WDT_CTL_RSTEN_Pos üÚ P WDT_CTL_RSTEN_Msk Ú P WDT_CTL_RSTF_Pos KÚ P WDT_CTL_RSTF_Msk RÚ P WDT_CTL_IF_Pos ÿÚ P WDT_CTL_IF_Msk Ú P WDT_CTL_WKEN_Pos UÚ P WDT_CTL_WKEN_Msk \Ú P WDT_CTL_WKF_Pos ¤Ú P WDT_CTL_WKF_Msk «Ú P WDT_CTL_INTEN_Pos
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Ú P WDT_CTL_INTEN_Msk Ú P WDT_CTL_WDTEN_Pos Ú P WDT_CTL_WDTEN_Msk
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Ú P WDT_CTL_TOUTSEL_Pos TÚ P WDT_CTL_TOUTSEL_Msk [Ú P WDT_CTL_ICEDEBUG_Pos JÚ P WDT_CTL_ICEDEBUG_Msk QÚ P WDT_ALTCTL_RSTDSEL_Pos |Ú P WDT_ALTCTL_RSTDSEL_Msk ƒÚ 8
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<unnamed> QÚ
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" ½RLDCNT 'Ú
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" ½CTL Ú
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" ½STATUS
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Ú
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" ½CNT Ú WWDT_T üÚ P WWDT_RLDCNT_RLDCNT_Pos |Ú P WWDT_RLDCNT_RLDCNT_Msk ƒÚ P WWDT_CTL_WWDTEN_Pos TÚ P WWDT_CTL_WWDTEN_Msk [Ú P WWDT_CTL_INTEN_Pos ±Ú P WWDT_CTL_INTEN_Msk ¸Ú P WWDT_CTL_PSCSEL_Pos cÚ P WWDT_CTL_PSCSEL_Msk jÚ P WWDT_CTL_CMPDAT_Pos tÚ P WWDT_CTL_CMPDAT_Msk {Ú P WWDT_CTL_ICEDEBUG_Pos ñÚ P WWDT_CTL_ICEDEBUG_Msk øÚ P WWDT_STATUS_WWDTIF_Pos QÚ P WWDT_STATUS_WWDTIF_Msk XÚ P WWDT_STATUS_WWDTRF_Pos HÚ P WWDT_STATUS_WWDTRF_Msk OÚ P WWDT_CNT_CNTDAT_Pos mÚ P WWDT_CNT_CNTDAT_Msk tÚ P FLASH_BASE ÏÚ P
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SRAM_BASE Ú P APB1PERIPH_BASE gÚ P APB2PERIPH_BASE fÚ P AHBPERIPH_BASE ¢Ú P WDT_BASE RÚ P
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WWDT_BASE ùÚ P TIMER0_BASE ŠÚ P TIMER1_BASE ‰Ú P
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I2C0_BASE QÚ P
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I2C1_BASE PÚ P SPI_BASE UÚ P PWM_BASE MÚ P UART0_BASE ÑÚ P UART1_BASE ÐÚ P
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ACMP_BASE Ú P ADC_BASE yÚ P SYS_BASE BÚ P CLK_BASE gÚ P
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INTR_BASE Ú P P0_BASE ÃÚ P P1_BASE ÂÚ P P2_BASE ÁÚ P P3_BASE ÀÚ P P4_BASE ¿Ú P P5_BASE ¾Ú P GPIO_DBNCECON_BASE cÚ P GPIO_PIN_DATA_BASE ?Ú P GPIOBIT0_BASE ùÚ P GPIOBIT1_BASE øÚ P GPIOBIT2_BASE ÷Ú P GPIOBIT3_BASE öÚ P GPIOBIT4_BASE õÚ P GPIOBIT5_BASE ôÚ P FMC_BASE kÚ P WDT ÖÚ
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P WWDT }Ú P TIMER0 Ú P TIMER1
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Ú P I2C Ú
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P I2C0 ÕÚ
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P I2C1 ÔÚ P SPI ÙÚ
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P SPI0 §Ú P PWM ÑÚ
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P UART ‡Ú P UART0 UÚ P UART1 TÚ P ADC ýÚ
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P ACMP ¢Ú P SYS ÆÚ P CLK ëÚ
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P INTR †Ú P P0 GÚ P P1 FÚ P P2 EÚ P P3 DÚ P P4 CÚ P P5 BÚ
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P GPIO ”Ú P FMC ïÚ vu8 ØÚ
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vu16 §Ú
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vu32 ©Ú P M8 BÚ P M16 Ú P M32 Ú P outpw ‚Ú
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P inpw Ú P outps †Ú
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P inps Ú P outpb —Ú
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P inpb Ú P outp32 ’Ú P inp32 Ú P outp16 �Ú P inp16 Ú P outp8 ÁÚ
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P inp8 DÚ
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P NULL ˆÚ
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P TRUE ƒÚ P FALSE VÚ P ENABLE Ú P DISABLE ÉÚ
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P BIT0 ´Ú
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P BIT1 ³Ú
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P BIT2 ²Ú
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P BIT3 ±Ú
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P BIT4 °Ú
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P BIT5 ¯Ú
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P BIT6 ®Ú
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P BIT7 Ú
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P BIT8 ¬Ú
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P BIT9 «Ú P BIT10 �Ú P BIT11 €Ú P BIT12 Ú P BIT13 ~Ú P BIT14 }Ú P BIT15 |Ú P BIT16 {Ú P BIT17 zÚ P BIT18 yÚ P BIT19 xÚ P BIT20 €Ú P BIT21 Ú P BIT22 ~Ú P BIT23 }Ú P BIT24 |Ú P BIT25 {Ú P BIT26 zÚ P BIT27 yÚ P BIT28 xÚ P BIT29 wÚ P BIT30 Ú P BIT31 ~Ú P
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BYTE0_Msk ËÚ P
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BYTE1_Msk ÊÚ P
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BYTE2_Msk ÉÚ P
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BYTE3_Msk ÈÚ P
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GET_BYTE0 Ú P
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GET_BYTE1 Ú P
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GET_BYTE2 Ú P
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GET_BYTE3 Ú P
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__SYS_H__ —Ú P ADC_RST �Ú P ACMP_RST BÚ P PWM0_RST ?Ú P
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UART0_RST õÚ P
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UART1_RST ôÚ P SPI0_RST GÚ P I2C0_RST uÚ P I2C1_RST tÚ P TMR1_RST ?Ú P TMR0_RST @Ú P GPIO_RST 4Ú P SYS_BODCTL_BOD_RST_EN
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Ú$ P SYS_BODCTL_BOD_INTERRUPT_EN -Ú P SYS_BODCTL_BODVL_4_4V 9Ú P SYS_BODCTL_BODVL_3_7V 7Ú P SYS_BODCTL_BODVL_2_7V 8Ú P SYS_BODCTL_BODVL_2_2V =Ú P SYS_MFP_TYPE_Msk ?Ú P SYS_MFP_ALT_Msk ¢Ú P SYS_MFP_MFP_Msk Ú P SYS_MFP_P00_GPIO ÍÚ P SYS_MFP_P00_UART0_nCTS ÍÚ P SYS_MFP_P00_UART0_TXD 7Ú P SYS_MFP_P00_Msk ÓÚ P SYS_MFP_P01_GPIO ÌÚ P SYS_MFP_P01_SPI0_SS ÔÚ P SYS_MFP_P01_UART0_nRTS ½Ú P SYS_MFP_P01_UART0_RXD 8Ú P SYS_MFP_P01_Msk ÒÚ P SYS_MFP_P04_GPIO ÉÚ P SYS_MFP_P04_PWM0_CH5 Ú P SYS_MFP_P04_SPI0_SS ÑÚ P SYS_MFP_P04_Msk ÏÚ P SYS_MFP_P05_GPIO ÈÚ P SYS_MFP_P05_PWM0_CH4 Ú P SYS_MFP_P05_SPI0_MOSI :Ú P SYS_MFP_P05_Msk ÎÚ P SYS_MFP_P06_GPIO ÇÚ P SYS_MFP_P06_PWM0_CH1 ¯Ú P SYS_MFP_P06_SPI0_MISO 9Ú P SYS_MFP_P06_Msk ÍÚ P SYS_MFP_P07_GPIO ÆÚ P SYS_MFP_P07_PWM0_CH0 ¯Ú P SYS_MFP_P07_SPI0_CLK ˜Ú P SYS_MFP_P07_Msk ÌÚ P SYS_MFP_P10_ACMP0_P1 ÂÚ P SYS_MFP_P10_ADC_CH1 Ú P SYS_MFP_P10_GPIO ÌÚ P SYS_MFP_P10_Msk ÒÚ P SYS_MFP_P12_ACMP0_P2 ¿Ú P SYS_MFP_P12_ADC_CH2 Ú P SYS_MFP_P12_GPIO ÊÚ P SYS_MFP_P12_UART0_RXD 6Ú P SYS_MFP_P12_PWM0_CH0 ³Ú P SYS_MFP_P12_Msk ÐÚ P SYS_MFP_P13_ACMP0_P3 ½Ú P SYS_MFP_P13_ADC_CH3
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Ú P SYS_MFP_P13_GPIO ÉÚ P SYS_MFP_P13_UART0_TXD 3Ú P SYS_MFP_P13_PWM0_CH1 ±Ú P SYS_MFP_P13_Msk ÏÚ P SYS_MFP_P14_ACMP0_N óÚ P SYS_MFP_P14_ADC_CH4 Ú P SYS_MFP_P14_GPIO ÈÚ P SYS_MFP_P14_UART1_RXD 3Ú P SYS_MFP_P14_PWM0_CH4 Ú P SYS_MFP_P14_Msk ÎÚ P SYS_MFP_P15_ACMP0_P0 ¾Ú P SYS_MFP_P15_ADC_CH5 Ú P SYS_MFP_P15_GPIO ÇÚ P SYS_MFP_P15_UART1_TXD 0Ú P SYS_MFP_P15_Msk ÍÚ P SYS_MFP_P22_GPIO ÉÚ P SYS_MFP_P22_I2C1_SCL ÀÚ P SYS_MFP_P22_PWM0_CH0 ²Ú P SYS_MFP_P22_Msk ÏÚ P SYS_MFP_P23_GPIO ÈÚ P SYS_MFP_P23_I2C1_SDA ÉÚ P SYS_MFP_P23_PWM0_CH1 °Ú P SYS_MFP_P23_Msk ÎÚ P SYS_MFP_P24_GPIO ÇÚ P SYS_MFP_P24_PWM0_CH2 ®Ú P SYS_MFP_P24_UART1_RXD 2Ú P SYS_MFP_P24_Msk ÍÚ P SYS_MFP_P25_GPIO ÆÚ P SYS_MFP_P25_PWM0_CH3 ¬Ú P SYS_MFP_P25_UART1_TXD /Ú P SYS_MFP_P25_Msk ÌÚ P SYS_MFP_P26_ACMP1_O îÚ P SYS_MFP_P26_GPIO ÅÚ P SYS_MFP_P26_PWM0_CH4 ªÚ P SYS_MFP_P26_Msk ËÚ P SYS_MFP_P30_ACMP1_N ôÚ P SYS_MFP_P30_ADC_CH6 Ú P SYS_MFP_P30_GPIO ÊÚ P SYS_MFP_P30_Msk ÐÚ P SYS_MFP_P31_ACMP1_P0 ¿Ú P SYS_MFP_P31_ADC_CH7 Ú P SYS_MFP_P31_GPIO ÉÚ P SYS_MFP_P31_Msk ÏÚ P SYS_MFP_P32_GPIO ÈÚ P SYS_MFP_P32_INT0 ÜÚ P SYS_MFP_P32_STADC †Ú P SYS_MFP_P32_TM0_EXT ÐÚ P SYS_MFP_P32_ACMP1_P1 ½Ú P SYS_MFP_P32_Msk ÎÚ P SYS_MFP_P34_ACMP1_P2 ºÚ P SYS_MFP_P34_GPIO ÆÚ P SYS_MFP_P34_I2C0_SDA ÈÚ P SYS_MFP_P34_TM0_CNT_OUT {Ú P SYS_MFP_P34_Msk ÌÚ P SYS_MFP_P35_ACMP1_P3 ¸Ú P SYS_MFP_P35_GPIO ÅÚ P SYS_MFP_P35_I2C0_SCL ½Ú P SYS_MFP_P35_TM1_CNT_OUT yÚ P SYS_MFP_P35_Msk ËÚ P SYS_MFP_P36_ACMP0_O îÚ P SYS_MFP_P36_CLKO ÊÚ P SYS_MFP_P36_GPIO ÄÚ P SYS_MFP_P36_TM1_EXT ËÚ P SYS_MFP_P36_Msk ÊÚ P SYS_MFP_P46_GPIO ÃÚ P SYS_MFP_P46_ICE_CLK âÚ P SYS_MFP_P46_UART1_RXD .Ú P SYS_MFP_P46_Msk ÉÚ P SYS_MFP_P47_GPIO ÂÚ P SYS_MFP_P47_ICE_DAT âÚ P SYS_MFP_P47_UART1_TXD +Ú P SYS_MFP_P47_Msk ÈÚ P SYS_MFP_P50_GPIO ÈÚ P SYS_MFP_P50_I2C1_SDA ÉÚ P SYS_MFP_P50_UART0_TXD 2Ú P SYS_MFP_P50_XT1_IN Ú P SYS_MFP_P50_Msk ÎÚ P SYS_MFP_P51_GPIO ÇÚ P SYS_MFP_P51_I2C1_SCL ¾Ú P SYS_MFP_P51_UART0_RXD 3Ú P SYS_MFP_P51_XT1_OUT ¼Ú P SYS_MFP_P51_Msk ÍÚ P SYS_MFP_P52_GPIO ÆÚ P SYS_MFP_P52_INT1 ÙÚ P SYS_MFP_P52_Msk ÌÚ P SYS_MFP_P53_ADC_CH
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u32Src ÑÚ SYS_ClearResetSrc VÚ SYS_GetBODStatus ñÚ SYS_GetResetSrc !Ú SYS_IsRegLocked @Ú
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SYS_ReadPDID ÕÚ SYS_ResetChip éÚ
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SYS_ResetCPU ‡Ú ,
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u32ModuleIndex ‹Ú SYS_ResetModule Ú , i32Mode €Ú ,
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u32BODLevel "Ú SYS_EnableBOD TÚ SYS_DisableBOD åÚ P
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__CLK_H__ ¼Ú P FREQ_25MHZ ÔÚ P FREQ_50MHZ ÖÚ P FREQ_72MHZ ÒÚ P FREQ_100MHZ ¨Ú P FREQ_200MHZ §Ú P FREQ_250MHZ ¢Ú P FREQ_500MHZ ¤Ú P CLK_PWRCTL_XTL12M �Ú P CLK_PWRCTL_XTLEN_HXT QÚ P CLK_PWRCTL_XTL32K �Ú P CLK_PWRCTL_XTLEN_LXT MÚ! P CLK_CLKSEL0_HCLKSEL_XTAL wÚ P CLK_CLKSEL0_HCLKSEL_HXT ¾Ú P CLK_CLKSEL0_HCLKSEL_LXT ºÚ P CLK_CLKSEL0_HCLKSEL_PLL ÊÚ! P CLK_CLKSEL0_HCLKSEL_LIRC †Ú! P CLK_CLKSEL0_HCLKSEL_HIRC ŠÚ" P CLK_CLKSEL0_STCLKSEL_XTAL Ú' P CLK_CLKSEL0_STCLKSEL_XTAL_DIV2 ˜Ú' P CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 ¯Ú' P CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 «Ú" P CLK_CLKSEL0_STCLKSEL_HCLK -Ú P CLK_CLKSEL1_WDTSEL_XTAL «Ú( P CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 ¢Ú" P CLK_CLKSEL1_WDTSEL_IRC10K VÚ P CLK_CLKSEL1_WDTSEL_LIRC ºÚ P CLK_CLKSEL1_ADCSEL_XTAL ÒÚ P CLK_CLKSEL1_ADCSEL_PLL %Ú P CLK_CLKSEL1_ADCSEL_HCLK éÚ P CLK_CLKSEL1_ADCSEL_HIRC åÚ P CLK_CLKSEL1_SPISEL_XTAL ®Ú P CLK_CLKSEL1_SPISEL_HCLK ÅÚ P CLK_CLKSEL1_SPISEL_PLL Ú! P CLK_CLKSEL1_TMR0SEL_XTAL uÚ! P CLK_CLKSEL1_TMR0SEL_LIRC „Ú! P CLK_CLKSEL1_TMR0SEL_HCLK ŒÚ P CLK_CLKSEL1_TMR0SEL_TM0 ßÚ! P CLK_CLKSEL1_TMR0SEL_HIRC ˆÚ! P CLK_CLKSEL1_TMR1SEL_XTAL tÚ! P CLK_CLKSEL1_TMR1SEL_LIRC ƒÚ! P CLK_CLKSEL1_TMR1SEL_HCLK ‹Ú P CLK_CLKSEL1_TMR1SEL_TM1 ÝÚ! P CLK_CLKSEL1_TMR1SEL_HIRC ‡Ú! P CLK_CLKSEL1_UARTSEL_XTAL \Ú P CLK_CLKSEL1_UARTSEL_PLL ¯Ú! P CLK_CLKSEL1_UARTSEL_HIRC oÚ$ P CLK_CLKSEL1_PWMCH01SEL_HCLK ÉÚ$ P CLK_CLKSEL1_PWMCH23SEL_HCLK ÅÚ! P CLK_CLKSEL2_CLKOSEL_XTAL nÚ P CLK_CLKSEL2_CLKOSEL_HXT µÚ P CLK_CLKSEL2_CLKOSEL_LXT ±Ú! P CLK_CLKSEL2_CLKOSEL_LIRC }Ú! P CLK_CLKSEL2_CLKOSEL_HCLK …Ú! P CLK_CLKSEL2_CLKOSEL_HIRC �Ú$ P CLK_CLKSEL2_PWMCH45SEL_HCLK ÀÚ) P !CLK_CLKSEL2_WWDTSEL_HCLK_DIV2048 HÚ! P CLK_CLKSEL2_WWDTSEL_LIRC `Ú P CLK_CLKDIV_ADC ’Ú P CLK_CLKDIV_UART Ú P CLK_CLKDIV_HCLK 6Ú P CLK_PLLCTL_PLLSRC_HXT Ú P CLK_PLLCTL_PLLSRC_HIRC çÚ P CLK_PLLCTL_NF ºÚ P CLK_PLLCTL_NR ®Ú P CLK_PLLCTL_NO_1 Ú P CLK_PLLCTL_NO_2 Ú P CLK_PLLCTL_NO_4 Ú P CLK_PLLCTL_72MHz_HXT uÚ P CLK_PLLCTL_96MHz_HXT oÚ P CLK_PLLCTL_100MHz_HXT KÚ P CLK_PLLCTL_72MHz_HIRC AÚ P CLK_PLLCTL_96MHz_HIRC ;Ú P CLK_PLLCTL_100MHz_HIRC Ú P MODULE_APBCLK ßÚ P MODULE_CLKSEL ÎÚ P MODULE_CLKSEL_Msk <Ú P MODULE_CLKSEL_Pos 5Ú P MODULE_CLKDIV ÏÚ P MODULE_CLKDIV_Msk =Ú P MODULE_CLKDIV_Pos 6Ú P MODULE_IP_EN_Pos jÚ P
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MODULE_NoMsk ¦Ú P NA 8Ú P MODULE_APBCLK_ENC ¢Ú P MODULE_CLKSEL_ENC ‘Ú P MODULE_CLKSEL_Msk_ENC ÿÚ P MODULE_CLKSEL_Pos_ENC øÚ P MODULE_CLKDIV_ENC ’Ú P MODULE_CLKDIV_Msk_ENC Ú P MODULE_CLKDIV_Pos_ENC ùÚ P MODULE_IP_EN_Pos_ENC -Ú P ISP_MODULE ¦Ú P WDT_MODULE £Ú P TMR0_MODULE mÚ P TMR1_MODULE lÚ P CLKO_MODULE gÚ P I2C0_MODULE ¢Ú P I2C1_MODULE ¡Ú P SPI0_MODULE tÚ P
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UART0_MODULE "Ú P
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UART1_MODULE !Ú P PWMCH01_MODULE ªÚ P PWMCH23_MODULE ¦Ú P PWMCH45_MODULE ¢Ú P ADC_MODULE ÊÚ P ACMP_MODULE oÚ P WWDT_MODULE JÚ CLK_GetPLLClockFreq Ú
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" ö u32PllFreq 2Ú
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" ö
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u32PllReg ¤Ú
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" öu32FIN Ú
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" öu32NF ^Ú
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" öu32NR RÚ
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" öu32NO UÚ <" ö au8NoTbl §Ú CLK_DisableCKO Ú ,
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u32ClkSrc ±Ú ,
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u32ClkDiv ¶Ú ,
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u32ClkDivBy1En
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Ú CLK_EnableCKO qÚ CLK_PowerDown ðÚ CLK_Idle !Ú CLK_GetHXTFreq ñÚ CLK_GetLXTFreq íÚ CLK_GetHCLKFreq ÁÚ CLK_GetCPUFreq ýÚ ,
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u32Hclk uÚ CLK_SetCoreClock îÚ ,
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u32ClkSrc ±Ú ,
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u32ClkDiv ¶Ú CLK_SetHCLK KÚ ,
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u32ModuleIdx bÚ ,
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u32ClkSrc ±Ú ,
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u32ClkDiv ¶Ú CLK_SetModuleClock
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Ú ,
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u32ClkSrc ±Ú CLK_SetSysTickClockSrc yÚ ,
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u32ClkSrc ±Ú ,
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u32Count ìÚ CLK_EnableSysTick |Ú CLK_DisableSysTick
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Ú ,
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u32ClkMask KÚ CLK_EnableXtalRC Ú ,
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u32ClkMask KÚ CLK_DisableXtalRC «Ú ,
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u32ModuleIdx bÚ CLK_EnableModuleClock ìÚ ,
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u32ModuleIdx bÚ CLK_DisableModuleClock }Ú ,
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us óÚ CLK_SysTickDelay ÖÚ ,
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u32PllClkSrc ƒÚ ,
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u32PllFreq ;Ú CLK_EnablePLL fÚ CLK_DisablePLL ÷Ú ,
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u32ClkMask KÚ CLK_WaitClockReady Ú P __ACMP_H__ sÚ P ACMP_VNEG_PIN »Ú P ACMP_VNEG_BANDGAP Ú P ACMP_VNEG_4_OVER_24_VDD ½Ú P ACMP_VNEG_5_OVER_24_VDD ¼Ú P ACMP_VNEG_6_OVER_24_VDD »Ú P ACMP_VNEG_7_OVER_24_VDD ºÚ P ACMP_VNEG_8_OVER_24_VDD ¹Ú P ACMP_VNEG_9_OVER_24_VDD ¸Ú! P ACMP_VNEG_10_OVER_24_VDD ŽÚ! P ACMP_VNEG_11_OVER_24_VDD �Ú! P ACMP_VNEG_12_OVER_24_VDD ŒÚ! P ACMP_VNEG_13_OVER_24_VDD ‹Ú! P ACMP_VNEG_14_OVER_24_VDD ŠÚ! P ACMP_VNEG_15_OVER_24_VDD ‰Ú! P ACMP_VNEG_16_OVER_24_VDD ˆÚ! P ACMP_VNEG_17_OVER_24_VDD ‡Ú! P ACMP_VNEG_18_OVER_24_VDD †Ú! P ACMP_VNEG_19_OVER_24_VDD …Ú P ACMP_HYSTERESIS_ENABLE Ú P ACMP_HYSTERESIS_DISABLE ·Ú P ACMP_CH0_POSPIN_P15 Ú P ACMP_CH0_POSPIN_P10 "Ú P ACMP_CH0_POSPIN_P12 Ú P ACMP_CH0_POSPIN_P13 Ú P ACMP_CH1_POSPIN_P31 Ú P ACMP_CH1_POSPIN_P32 Ú P ACMP_CH1_POSPIN_P34 Ú P ACMP_CH1_POSPIN_P35 Ú P ACMP_FILTSEL_OFF ÞÚ P ACMP_FILTSEL_1PCLK ZÚ P ACMP_FILTSEL_2PCLK YÚ P ACMP_FILTSEL_4PCLK WÚ P ACMP_FILTSEL_8PCLK SÚ P ACMP_FILTSEL_16PCLK "Ú P ACMP_FILTSEL_32PCLK $Ú P ACMP_FILTSEL_64PCLK Ú P ACMP_FILTSEL_128PCLK ìÚ P ACMP_FILTSEL_256PCLK êÚ P ACMP_FILTSEL_512PCLK ïÚ P ACMP_SET_NEG_SRC ¿Ú P ACMP_ENABLE_HYSTERESIS Ú P ACMP_DISABLE_HYSTERESIS ·Ú P ACMP_ENABLE_INT <Ú P ACMP_DISABLE_INT íÚ P ACMP_ENABLE ŽÚ P
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ACMP_DISABLE ?Ú P ACMP_GET_OUTPUT ýÚ P ACMP_GET_INT_FLAG †Ú P ACMP_CLR_INT_FLAG …Ú P ACMP_SELECT_P ÂÚ P
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ACMP_CRV_SEL Ú P ACMP_ENABLE_CRV <Ú P ACMP_DISABLE_CRV íÚ) P !ACMP_ENABLE_FALLING_EDGE_TRIGGER !Ú* P "ACMP_DISABLE_FALLING_EDGE_TRIGGER ÒÚ( P ACMP_ENABLE_RISING_EDGE_TRIGGER TÚ) P !ACMP_DISABLE_RISING_EDGE_TRIGGER Ú P ACMP_SET_FILTER Ú
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, acmp (Ú ,
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u32ChNum Ú ,
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u32NegSrc ±Ú ,
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u32HysteresisEn Ú
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ACMP_Open ÄÚ
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, acmp (Ú ,
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u32ChNum Ú ACMP_Close ^Ú P
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__ADC_H__ ÎÚ P ADC_CH7_EXT |Ú P ADC_CH7_BGP ”Ú P ADC_CMP0_LESS_THAN PÚ P ADC_CMP1_LESS_THAN OÚ% P ADC_CMP0_GREATER_OR_EQUAL_TO Ú% P ADC_CMP1_GREATER_OR_EQUAL_TO Ú P ADC_TRIGGER_BY_EXT_PIN ÔÚ P ADC_TRIGGER_BY_PWM Ú! P ADC_FALLING_EDGE_TRIGGER �Ú P ADC_RISING_EDGE_TRIGGER ÃÚ P
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ADC_ADIF_INT .Ú P
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ADC_CMP0_INT 2Ú P
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ADC_CMP1_INT 1Ú P ADC_SAMPLE_CLOCK_0 dÚ P ADC_SAMPLE_CLOCK_1 cÚ P ADC_SAMPLE_CLOCK_2 bÚ P ADC_SAMPLE_CLOCK_4 `Ú P ADC_SAMPLE_CLOCK_8 \Ú P ADC_SAMPLE_CLOCK_16 +Ú P ADC_SAMPLE_CLOCK_32 -Ú P ADC_SAMPLE_CLOCK_64 (Ú P ADC_SAMPLE_CLOCK_128 õÚ P ADC_SAMPLE_CLOCK_256 óÚ P ADC_SAMPLE_CLOCK_512 øÚ P ADC_SAMPLE_CLOCK_1024 ÇÚ! P ADC_SEQMODE_TYPE_23SHUNT oÚ P ADC_SEQMODE_TYPE_1SHUNT ¥Ú$ P ADC_SEQMODE_MODESELECT_CH01 ÑÚ$ P ADC_SEQMODE_MODESELECT_CH12 ÏÚ$ P ADC_SEQMODE_MODESELECT_CH02 ÐÚ P ADC_SEQMODE_PWM0_RISING ºÚ P ADC_SEQMODE_PWM0_CENTER ÅÚ! P ADC_SEQMODE_PWM0_FALLING ‡Ú P ADC_SEQMODE_PWM0_PERIOD ÃÚ P ADC_SEQMODE_PWM2_RISING ¸Ú P ADC_SEQMODE_PWM2_CENTER ÃÚ! P ADC_SEQMODE_PWM2_FALLING …Ú P ADC_SEQMODE_PWM2_PERIOD ÁÚ P ADC_SEQMODE_PWM4_RISING ¶Ú P ADC_SEQMODE_PWM4_CENTER ÁÚ! P ADC_SEQMODE_PWM4_FALLING ƒÚ P ADC_SEQMODE_PWM4_PERIOD ¿Ú P ADC_CONFIG_CH7 ±Ú P ADC_GET_CONVERSION_DATA ¸Ú P ADC_GET_INT_FLAG áÚ P ADC_CLR_INT_FLAG àÚ P ADC_IS_BUSY PÚ P ADC_IS_DATA_OVERRUN ÙÚ P ADC_IS_DATA_VALID žÚ P ADC_POWER_DOWN dÚ P
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ADC_POWER_ON Ú P ADC_ENABLE_CMP0 pÚ P ADC_DISABLE_CMP0 !Ú P ADC_ENABLE_CMP1 oÚ P ADC_DISABLE_CMP1 Ú P ADC_SET_INPUT_CHANNEL GÚ P ADC_START_CONV eÚ P ADC_STOP_CONV ¯Ú , adc £Ú ,
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u32InputMode XÚ ,
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u32OpMode ¯Ú ,
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u32ChMask ¼Ú ADC_Open Ú , adc £Ú
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ADC_Close ¹Ú , adc £Ú ,
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u32Source ‚Ú ,
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u32Param Ú ADC_EnableHWTrigger áÚ , adc £Ú ADC_DisableHWTrigger rÚ , adc £Ú ,
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u32ChNum Ú ,
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u32SampleTime úÚ ADC_SetExtraSampleTime tÚ , adc £Ú ,
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u32Mask kÚ ADC_EnableInt 5Ú , adc £Ú ,
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u32Mask kÚ ADC_DisableInt ÆÚ , adc £Ú ,
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u32SeqTYPE †Ú ,
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u32ModeSel HÚ ADC_SeqModeEnable ªÚ , adc £Ú ,
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u32SeqModeTriSrc1 Ú ,
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u32SeqModeTriSrc2 ¬Ú ADC_SeqModeTriggerSrc íÚ P
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__FMC_H__ ÀÚ P FMC_APROM_BASE �Ú P FMC_APROM_END ÇÚ P FMC_LDROM_BASE ‚Ú P FMC_LDROM_END ÈÚ P FMC_SPROM_BASE oÚ P FMC_SPROM_END µÚ P FMC_CONFIG_BASE HÚ P FMC_FLASH_PAGE_SIZE ìÚ P FMC_LDROM_SIZE bÚ P FMC_SPROM_SIZE OÚ P FMC_ISPCMD_READ =Ú P FMC_ISPCMD_READ_UID ôÚ P FMC_ISPCMD_READ_CID Ú P FMC_ISPCMD_READ_PID ùÚ P FMC_ISPCMD_READ_CRC32 •Ú P FMC_ISPCMD_PROGRAM ;Ú P FMC_ISPCMD_PAGE_ERASE aÚ P FMC_ISPCMD_CAL_CRC32 ãÚ P FMC_ISPCMD_VECMAP ™Ú P FMC_SET_APROM_BOOT Ú P FMC_SET_LDROM_BOOT Ú P FMC_DISABLE_AP_UPDATE fÚ P FMC_DISABLE_SP_UPDATE TÚ P FMC_DISABLE_CFG_UPDATE %Ú P FMC_DISABLE_LD_UPDATE gÚ P FMC_DISABLE_ISP 9Ú P FMC_ENABLE_AP_UPDATE µÚ P FMC_ENABLE_SP_UPDATE £Ú P FMC_ENABLE_LD_UPDATE ¶Ú P FMC_ENABLE_CFG_UPDATE tÚ P FMC_ENABLE_ISP ˆÚ P FMC_GET_FAIL_FLAG Ú
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FMC_Close «Ú ,
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u32PageAddr ÷Ú
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FMC_Erase ±Ú FMC_GetBootSource lÚ FMC_Open Ú ,
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u32Addr |Ú FMC_Read 'Ú FMC_ReadCID QÚ FMC_ReadPID DÚ ,
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u32Index ýÚ
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FMC_ReadUCID úÚ ,
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u32Index ýÚ FMC_ReadUID ?Ú" FMC_ReadDataFlashBaseAddr §Ú ,
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u32PageAddr ÷Ú FMC_SetVectorPageAddr òÚ FMC_GetVectorPageAddr þÚ ,
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u32Addr |Ú ,
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u32Data }Ú
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FMC_Write –Ú ,
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u32Config �Ú ,
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u32Count ìÚ FMC_ReadConfig ÅÚ ,
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u32Config �Ú ,
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u32Count ìÚ FMC_WriteConfig 4Ú
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,
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addr <Ú ,
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count ¬Ú , chksum :Ú FMC_GetCRC32Sum Ú P __GPIO_H__ eÚ P
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GPIO_PIN_MAX ùÚ P GPIO_MODE_INPUT Ú P GPIO_MODE_OUTPUT ¨Ú P GPIO_MODE_OPEN_DRAIN ’Ú P GPIO_MODE_QUASI Ú P GPIO_INT_RISING Ú P GPIO_INT_FALLING ÖÚ P GPIO_INT_BOTH_EDGE .Ú P GPIO_INT_HIGH ¹Ú P
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GPIO_INT_LOW éÚ P GPIO_INTTYPE_EDGE zÚ P GPIO_INTTYPE_LEVEL Ú P GPIO_DBCTL_ICLK_ON 2Ú P GPIO_DBCTL_ICLK_OFF òÚ# P GPIO_DBCTL_DBCLKSRC_IRC10K Ú! P GPIO_DBCTL_DBCLKSRC_HCLK |Ú P GPIO_DBCTL_DBCLKSEL_1 wÚ P GPIO_DBCTL_DBCLKSEL_2 vÚ P GPIO_DBCTL_DBCLKSEL_4 tÚ P GPIO_DBCTL_DBCLKSEL_8 pÚ P GPIO_DBCTL_DBCLKSEL_16 ?Ú P GPIO_DBCTL_DBCLKSEL_32 AÚ P GPIO_DBCTL_DBCLKSEL_64 <Ú P GPIO_DBCTL_DBCLKSEL_128 Ú P GPIO_DBCTL_DBCLKSEL_256 Ú P GPIO_DBCTL_DBCLKSEL_512 Ú! P GPIO_DBCTL_DBCLKSEL_1024 ÛÚ! P GPIO_DBCTL_DBCLKSEL_2048 ÔÚ! P GPIO_DBCTL_DBCLKSEL_4096 ÏÚ! P GPIO_DBCTL_DBCLKSEL_8192 ÎÚ" P GPIO_DBCTL_DBCLKSEL_16384 šÚ" P GPIO_DBCTL_DBCLKSEL_32768 –Ú P GPIO_PIN_ADDR ÂÚ P P00 Ú P P01 Ú P P02 Ú P P03 Ú P P04 Ú P P05 Ú P P06 Ú P P07 Ú P P10 Ú P P11 Ú P P12 Ú P P13 Ú P P14 Ú P P15 Ú P P16 Ú P P17
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Ú P P20 Ú P P21 Ú P P22 Ú P P23 Ú P P24 Ú P P25 Ú P P26
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Ú P P27 Ú P P30 Ú P P31 Ú P P32 Ú P P33 Ú P P34 Ú P P35
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Ú P P36 Ú P P37 Ú P P40 Ú P P41 Ú P P42 Ú P P43 Ú P P44
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Ú P P45 Ú P P46 Ú P P47
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Ú P P50 Ú P P51 Ú P P52 Ú P P53
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Ú P P54 Ú P P55 Ú P GPIO_CLR_INT_FLAG wÚ P GPIO_DISABLE_DEBOUNCE {Ú P GPIO_ENABLE_DEBOUNCE ÊÚ" P GPIO_DISABLE_DIGITAL_PATH .Ú! P GPIO_ENABLE_DIGITAL_PATH }Ú P GPIO_DISABLE_DOUT_MASK ÷Ú P GPIO_ENABLE_DOUT_MASK FÚ P GPIO_GET_INT_FLAG xÚ P GPIO_SET_DEBOUNCE_TIME óÚ P GPIO_GET_IN_DATA ÎÚ P GPIO_SET_OUT_DATA _Ú P GPIO_TOGGLE eÚ P GPIO_EnableEINT0 vÚ P GPIO_DisableEINT0 Ú P GPIO_EnableEINT1 uÚ P GPIO_DisableEINT1 Ú
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, gpio Ú ,
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u32PinMask >Ú ,
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u32Mode rÚ
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GPIO_SetMode ‘Ú
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, gpio Ú ,
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u32Pin ÒÚ ,
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u32IntAttribs çÚ GPIO_EnableInt ÌÚ
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, gpio Ú ,
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u32Pin ÒÚ GPIO_DisableInt ]Ú P
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__I2C_H__ ØÚ P I2C_STA ¸Ú P I2C_STO ªÚ P I2C_SI Ú P I2C_AA Ú P I2C_SET_CONTROL_REG ßÚ P
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I2C_START Ú P I2C_STOP XÚ P I2C_WAIT_READY ‰Ú P I2C_DISABLE_FIFO Ú P I2C_ENABLE_FIFO fÚ" P I2C_DISABLE_CLOCK_STRETCH AÚ! P I2C_ENABLE_CLOCK_STRETCH �Ú P I2C_DISABLE_OVERRUN_INT ²Ú P I2C_ENABLE_OVERRUN_INT Ú P I2C_ENABLE_UNDERRUN_INT ½Ú! P I2C_DISABLE_UNDERRUN_INT nÚ P
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I2C_GET_DATA =Ú P
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I2C_SET_DATA 1Ú P I2C_GET_STATUS oÚ P I2C_GET_TIMEOUT_FLAG §Ú P I2C_GET_WAKEUP_FLAG Ú P I2C_CLEAR_WAKEUP_FLAG xÚ , i2c ÍÚ ,
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u32BusClock ÙÚ I2C_Open )Ú , i2c ÍÚ
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I2C_Close ÃÚ , i2c ÍÚ I2C_ClearTimeoutFlag [Ú , i2c ÍÚ , u8Start Ú , u8Stop ‡Ú
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, u8Si uÚ , u8Ack Ú I2C_Trigger áÚ , i2c ÍÚ I2C_DisableInt ÐÚ , i2c ÍÚ I2C_EnableInt ?Ú , i2c ÍÚ I2C_GetBusClockFreq áÚ , i2c ÍÚ ,
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u32BusClock ÙÚ I2C_SetBusClockFreq ÕÚ , i2c ÍÚ I2C_GetIntFlag êÚ , i2c ÍÚ I2C_GetStatus
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2021-10-07 09:32:05 +08:00
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Ú , i2c ÍÚ I2C_GetData Ú , i2c ÍÚ , u8Data ³Ú I2C_SetData Ú , i2c ÍÚ ,
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u8SlaveNo oÚ , u8SlaveAddr Ú , u8GCMode Ú I2C_SetSlaveAddr Ú , i2c ÍÚ ,
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2021-09-26 17:18:47 +08:00
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u8SlaveNo oÚ , u8SlaveAddrMask Ú I2C_SetSlaveAddrMask uÚ , i2c ÍÚ , u8LongTimeout ¨Ú I2C_EnableTimeout {Ú , i2c ÍÚ I2C_DisableTimeout Ú , i2c ÍÚ I2C_EnableWakeup ÷Ú , i2c ÍÚ I2C_DisableWakeup ˆÚ P
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__PWM_H__ ¢Ú P PWM_CHANNEL_NUM Ú P PWM_CLK_DIV_1 ²Ú P PWM_CLK_DIV_2 ±Ú P PWM_CLK_DIV_4 ¯Ú P PWM_CLK_DIV_8 «Ú P PWM_CLK_DIV_16 zÚ P PWM_EDGE_ALIGNED ðÚ P PWM_CENTER_ALIGNED @Ú" P PWM_TRIGGER_ADC_CNTR_IS_0 ëÚ& P PWM_TRIGGER_ADC_CNTR_IS_CMR_D ŽÚ$ P PWM_TRIGGER_ADC_CNTR_IS_CNR 4Ú& P PWM_TRIGGER_ADC_CNTR_IS_CMR_U }Ú P PWM_FB0_EINT0 çÚ P PWM_FB0_ACMP1 õÚ P PWM_FB1_EINT1 åÚ P PWM_FB1_ACMP0 õÚ! P PWM_PERIOD_INT_UNDERFLOW &Ú! P PWM_PERIOD_INT_MATCH_CNR -Ú P PWM_CH0 ¯Ú P PWM_CH1 ®Ú P PWM_CH2 Ú P PWM_CH3 ¬Ú P PWM_CH4 «Ú P PWM_CH5 ªÚ& P PWM_ENABLE_COMPLEMENTARY_MODE ÔÚ' P PWM_DISABLE_COMPLEMENTARY_MODE …Ú P PWM_ENABLE_GROUP_MODE 7Ú P PWM_DISABLE_GROUP_MODE èÚ P PWM_ENABLE_SYNC_MODE ‰Ú P PWM_DISABLE_SYNC_MODE :Ú# P PWM_ENABLE_OUTPUT_INVERTER Ú P PWM_SET_PRESCALER jÚ P PWM_SET_DIVIDER Ú P PWM_SET_CMR 5Ú P PWM_SET_CNR 4Ú P
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PWM_SET_CMRD ïÚ P PWM_SET_ALIGNED_TYPE pÚ# P PWM_ENABLE_ASYMMETRIC_MODE ¼Ú P PWM_ENABLE_PCAEN ëÚ , pwm wÚ ,
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u32ChannelNum Ú ,
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u32Frequency ;Ú ,
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2021-10-07 09:32:05 +08:00
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u32DutyCycle WÚ PWM_ConfigOutputChannel ÇÚ , pwm wÚ ,
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2021-09-26 17:18:47 +08:00
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u32ChannelMask ¤Ú
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PWM_Start uÚ , pwm wÚ ,
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u32ChannelMask ¤Ú PWM_Stop ßÚ , pwm wÚ ,
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u32ChannelMask ¤Ú PWM_ForceStop æÚ , pwm wÚ ,
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u32ChannelNum Ú ,
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u32Condition FÚ PWM_EnableADCTrigger ŠÚ , pwm wÚ ,
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u32ChannelNum Ú PWM_DisableADCTrigger Ú , pwm wÚ ,
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u32ChannelNum Ú ,
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u32Condition FÚ PWM_ClearADCTriggerFlag jÚ , pwm wÚ ,
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u32ChannelNum Ú ,
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u32Condition FÚ PWM_GetADCTriggerFlag 5Ú , pwm wÚ ,
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u32ChannelMask ¤Ú ,
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u32LevelMask iÚ ,
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u32BrakeSource “Ú PWM_EnableFaultBrake EÚ , pwm wÚ ,
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u32BrakeSource “Ú PWM_ClearFaultBrakeFlag %Ú , pwm wÚ ,
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u32ChannelMask ¤Ú PWM_EnableOutput �Ú , pwm wÚ ,
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u32ChannelMask ¤Ú PWM_DisableOutput .Ú , pwm wÚ ,
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u32ChannelNum Ú ,
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u32Duration ©Ú PWM_EnableDeadZone Ú , pwm wÚ ,
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u32ChannelNum Ú PWM_DisableDeadZone ±Ú , pwm wÚ ,
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u32ChannelNum Ú ,
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u32IntDutyType vÚ PWM_EnableDutyInt [Ú , pwm wÚ ,
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u32ChannelNum Ú PWM_DisableDutyInt ìÚ , pwm wÚ ,
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u32ChannelNum Ú PWM_ClearDutyIntFlag ;Ú , pwm wÚ ,
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u32ChannelNum Ú PWM_GetDutyIntFlag Ú , pwm wÚ ,
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u32BrakeSource “Ú PWM_EnableFaultBrakeInt Ú , pwm wÚ ,
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u32BrakeSource “Ú! PWM_DisableFaultBrakeInt ¥Ú , pwm wÚ ,
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u32BrakeSource “Ú# PWM_ClearFaultBrakeIntFlag ôÚ , pwm wÚ ,
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2021-10-07 09:32:05 +08:00
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u32BrakeSource “Ú! PWM_GetFaultBrakeIntFlag ¿Ú , pwm wÚ ,
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u32ChannelNum Ú PWM_EnablePeriodInt šÚ , pwm wÚ ,
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2021-09-26 17:18:47 +08:00
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u32ChannelNum Ú PWM_DisablePeriodInt +Ú , pwm wÚ ,
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u32ChannelNum Ú PWM_ClearPeriodIntFlag zÚ , pwm wÚ ,
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u32ChannelNum Ú PWM_GetPeriodIntFlag EÚ , pwm wÚ ,
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u32ChannelNum Ú ,
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u32IntPeriodType µÚ PWM_EnableCenterInt œÚ , pwm wÚ ,
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u32ChannelNum Ú PWM_DisableCenterInt -Ú , pwm wÚ ,
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u32ChannelNum Ú PWM_ClearCenterIntFlag |Ú , pwm wÚ ,
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u32ChannelNum Ú PWM_GetCenterIntFlag GÚ , pwm wÚ ,
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u32ChannelNum Ú PWM_EnableRiseInt nÚ , pwm wÚ ,
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u32ChannelNum Ú PWM_DisableRiseInt ÿÚ , pwm wÚ ,
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u32ChannelNum Ú PWM_ClearRiseIntFlag NÚ , pwm wÚ ,
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u32ChannelNum Ú PWM_GetRiseIntFlag Ú P
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__SPI_H__ ªÚ P SPI_MODE_0 ¸Ú P SPI_MODE_1 ·Ú P SPI_MODE_2 ¶Ú P SPI_MODE_3 µÚ P
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SPI_SLAVE óÚ P SPI_MASTER Ú P SPI_SS ÎÚ P SPI_SS_ACTIVE_HIGH Ú P SPI_SS_ACTIVE_LOW LÚ P SPI_IE_MASK QÚ P SPI_SSTA_INTEN_MASK ·Ú P SPI_FIFO_TX_INTEN_MASK ½Ú P SPI_FIFO_RX_INTEN_MASK ¿Ú! P SPI_FIFO_RXOV_INTEN_MASK Ú$ P SPI_FIFO_TIMEOUT_INTEN_MASK 8Ú! P SPI_ABORT_3WIRE_TRANSFER KÚ% P SPI_CLR_3WIRE_START_INT_FLAG îÚ$ P SPI_CLR_UNIT_TRANS_INT_FLAG Ú P SPI_DISABLE_3WIRE_MODE Ú P SPI_ENABLE_3WIRE_MODE bÚ P SPI_GET_RX_FIFO_COUNT Ú# P SPI_GET_RX_FIFO_EMPTY_FLAG yÚ# P SPI_GET_TX_FIFO_EMPTY_FLAG wÚ" P SPI_GET_TX_FIFO_FULL_FLAG ÕÚ P SPI_READ_RX EÚ P
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SPI_WRITE_TX ÒÚ SPI_SET_SS_HIGH Ú ," êspi YÚ SPI_SET_SS_LOW KÚ ," ìspi WÚ P SPI_ENABLE_BYTE_REORDER ¦Ú! P SPI_DISABLE_BYTE_REORDER WÚ P SPI_SET_SUSPEND_CYCLE Ú P SPI_SET_LSB_FIRST KÚ P SPI_SET_MSB_FIRST JÚ SPI_SET_DATA_WIDTH AÚ ," óspi PÚ ,
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" ó u32Width ÆÚ P SPI_IS_BUSY ,Ú P SPI_TRIGGER VÚ , spi Ú ,
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u32MasterSlave ‚Ú ,
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u32SPIMode €Ú ,
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u32DataWidth sÚ ,
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u32BusClock ÙÚ SPI_Open ûÚ , spi Ú
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SPI_Close •Ú , spi Ú SPI_ClearRxFIFO ªÚ , spi Ú SPI_ClearTxFIFO ¨Ú , spi Ú SPI_DisableAutoSS ˆÚ , spi Ú ,
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u32SSPinMask ”Ú ,
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u32ActiveLevel •Ú SPI_EnableAutoSS ÷Ú , spi Ú ,
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u32BusClock ÙÚ SPI_SetBusClock =Ú , spi Ú ,
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u32TxThreshold pÚ ,
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u32RxThreshold rÚ SPI_EnableFIFO Ú , spi Ú SPI_DisableFIFO §Ú , spi Ú SPI_GetBusClock IÚ , spi Ú ,
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u32Mask kÚ SPI_EnableInt Ú , spi Ú ,
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u32Mask kÚ SPI_DisableInt ¢Ú P __TIMER_H__ Ú P TIMER_ONESHOT_MODE #Ú P TIMER_PERIODIC_MODE òÚ P TIMER_TOGGLE_MODE ƒÚ P TIMER_CONTINUOUS_MODE &Ú) P !TIMER_CAPTURE_FREE_COUNTING_MODE ÌÚ, P $TIMER_CAPTURE_TRIGGER_COUNTING_MODE ÔÚ) P !TIMER_CAPTURE_COUNTER_RESET_MODE ²Ú# P TIMER_CAPTURE_FALLING_EDGE ÓÚ" P TIMER_CAPTURE_RISING_EDGE Ú/ P 'TIMER_CAPTURE_FALLING_THEN_RISING_EDGE Ú/ P 'TIMER_CAPTURE_RISING_THEN_FALLING_EDGE Ú" P TIMER_COUNTER_RISING_EDGE úÚ# P TIMER_COUNTER_FALLING_EDGE ÇÚ! P TIMER_TOGGLE_TMX_CNT_OUT Ú P TIMER_TOGGLE_TMX_EXT YÚ P TIMER_SET_CMP_VALUE ¾Ú! P TIMER_SET_PRESCALE_VALUE EÚ P TIMER_IS_ACTIVE Ú P TIMER_SELECT_TOUT_PIN Ú TIMER_Start ðÚ ," ¯timer ºÚ TIMER_Stop ZÚ ," ±timer ¸Ú TIMER_EnableWakeup <Ú ," ³timer ¶Ú TIMER_DisableWakeup ÍÚ ," µtimer ´Ú$ TIMER_EnableCaptureDebounce žÚ ," ·timer ²Ú% TIMER_DisableCaptureDebounce /Ú ," ¹timer °Ú) !TIMER_EnableEventCounterDebounce †Ú ," »timer ®Ú* "TIMER_DisableEventCounterDebounce Ú ," ½timer ¬Ú TIMER_EnableInt „Ú ," ¿timer ªÚ TIMER_DisableInt Ú ," Átimer ¨Ú TIMER_EnableCaptureInt ¢Ú ," Ãtimer ¦Ú TIMER_DisableCaptureInt 3Ú ," Åtimer ¤Ú TIMER_GetIntFlag /Ú ," Çtimer ¢Ú TIMER_ClearIntFlag dÚ ," Étimer Ú TIMER_GetCaptureIntFlag MÚ ," Ëtimer žÚ" TIMER_ClearCaptureIntFlag ‚Ú ," Ítimer œÚ TIMER_GetWakeupFlag çÚ ," Ïtimer šÚ TIMER_ClearWakeupFlag Ú ," Ñtimer ˜Ú TIMER_GetCaptureData ~Ú ," Ótimer –Ú TIMER_GetCounter ôÚ ," Õtimer ”Ú , timer ¦Ú ,
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u32Mode rÚ ,
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u32Freq iÚ TIMER_Open bÚ , timer ¦Ú TIMER_Close üÚ , timer ¦Ú ,
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u32Usec gÚ TIMER_Delay Ú , timer ¦Ú ,
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u32CapMode XÚ ,
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u32Edge ‚Ú TIMER_EnableCapture ÇÚ , timer ¦Ú TIMER_DisableCapture XÚ , timer ¦Ú ,
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u32Edge ‚Ú! TIMER_EnableEventCounter ¯Ú , timer ¦Ú" TIMER_DisableEventCounter @Ú , timer ¦Ú TIMER_GetModuleClock nÚ P __UART_H__ XÚ P UART_FIFO_RFITL_1BYTE >Ú P UART_FIFO_RFITL_4BYTES æÚ P UART_FIFO_RFITL_8BYTES âÚ P UART_FIFO_RFITL_14BYTES ³Ú! P UART_FIFO_RTSTRGLV_1BYTE 1Ú" P UART_FIFO_RTSTRGLV_4BYTES ÙÚ" P UART_FIFO_RTSTRGLV_8BYTES ÕÚ# P UART_FIFO_RTSTRGLV_14BYTES ¦Ú P UART_WORD_LEN_5 Ú P UART_WORD_LEN_6 Ú P UART_WORD_LEN_7 Ú P UART_WORD_LEN_8 Ú P UART_PARITY_NONE ¨Ú P UART_PARITY_ODD Ú P UART_PARITY_EVEN ªÚ P UART_PARITY_MARK Ú P UART_PARITY_SPACE jÚ P UART_STOP_BIT_1 þÚ P UART_STOP_BIT_1_5 fÚ P UART_STOP_BIT_2 ýÚ! P UART_RTS_IS_HIGH_LEV_TRG ûÚ P UART_RTS_IS_LOW_LEV_TRG +Ú P UART_FUNC_SEL_UART Ú P UART_FUNC_SEL_IrDA þÚ P UART_FUNC_SEL_RS485 öÚ P UART_BAUD_MODE0 BÚ P UART_BAUD_MODE2 @Ú P UART_BAUD_MODE0_DIVIDER ÌÚ P UART_BAUD_MODE2_DIVIDER ÊÚ P UART_WRITE ‘Ú P
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UART_READ Ú P UART_GET_TX_EMPTY 5Ú P UART_GET_RX_EMPTY 7Ú P UART_IS_TX_EMPTY {Ú P UART_WAIT_TX_EMPTY ÞÚ P UART_IS_RX_READY —Ú P UART_IS_TX_FULL ÙÚ P UART_IS_RX_FULL ÛÚ P UART_GET_TX_FULL “Ú P UART_GET_RX_FULL •Ú P UART_ENABLE_INT !Ú P UART_DISABLE_INT ÒÚ P UART_GET_INT_FLAG kÚ UART_CLEAR_RTS rÚ ," ™ uart 6Ú
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UART_SET_RTS ñÚ ," › uart 4Ú# P UART_RS485_CLEAR_ADDR_FLAG ýÚ! P UART_RS485_GET_ADDR_FLAG ˆÚ
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, uart
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Ú ,
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u32InterruptFlag žÚ UART_ClearIntFlag ŸÚ
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, uart
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Ú UART_Close CÚ
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, uart
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Ú UART_DisableFlowCtrl DÚ
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, uart
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Ú ,
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u32InterruptFlag žÚ UART_DisableInt PÚ
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, uart
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Ú UART_EnableFlowCtrl ³Ú
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, uart
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Ú ,
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u32InterruptFlag žÚ UART_EnableInt ¿Ú
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, uart
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Ú ,
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u32baudrate §Ú
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UART_Open ©Ú
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, uart
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Ú , pu8RxBuf ½Ú ,
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u32ReadBytes jÚ
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UART_Read ¿Ú
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, uart
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Ú ,
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u32baudrate §Ú ,
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u32data_width ÒÚ ,
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2021-10-07 09:32:05 +08:00
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u32parity ZÚ ,
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2021-09-26 17:18:47 +08:00
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u32stop_bits Ú UART_SetLine_Config ¾Ú
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, uart
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Ú ,
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u32TOC Ú UART_SetTimeoutCnt ñÚ
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, uart
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Ú ,
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u32Buadrate ÇÚ ,
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u32Direction LÚ UART_SelectIrDAMode Ú
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, uart
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Ú ,
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u32Mode rÚ ,
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u32Addr |Ú UART_SelectRS485Mode úÚ
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, uart
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Ú , pu8TxBuf »Ú ,
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u32WriteBytes ÙÚ UART_Write .Ú P
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__WDT_H__ §Ú P WDT_TIMEOUT_2POW4 yÚ P WDT_TIMEOUT_2POW6 wÚ P WDT_TIMEOUT_2POW8 uÚ P WDT_TIMEOUT_2POW10 JÚ P WDT_TIMEOUT_2POW12 HÚ P WDT_TIMEOUT_2POW14 FÚ P WDT_TIMEOUT_2POW16 DÚ P WDT_TIMEOUT_2POW18 BÚ P WDT_RESET_DELAY_3CLK ˜Ú P WDT_RESET_DELAY_18CLK `Ú P WDT_RESET_DELAY_130CLK 3Ú P WDT_RESET_DELAY_1026CLK üÚ P WDT_CLEAR_RESET_FLAG “Ú# P WDT_CLEAR_TIMEOUT_INT_FLAG ™Ú& P WDT_CLEAR_TIMEOUT_WAKEUP_FLAG ±Ú P WDT_GET_RESET_FLAG Ú! P WDT_GET_TIMEOUT_INT_FLAG $Ú$ P WDT_GET_TIMEOUT_WAKEUP_FLAG <Ú P WDT_RESET_COUNTER YÚ ,
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u32TimeoutInterval µÚ ,
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u32ResetDelay ùÚ ,
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u32EnableReset ŸÚ ,
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u32EnableWakeup 3Ú WDT_Open øÚ
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WDT_Close ’Ú WDT_EnableInt Ú WDT_DisableInt ŸÚ P __WWDT_H__ NÚ P WWDT_PRESCALER_1 ÕÚ P WWDT_PRESCALER_2 ÔÚ P WWDT_PRESCALER_4 ÒÚ P WWDT_PRESCALER_8 ÎÚ P WWDT_PRESCALER_16 �Ú P WWDT_PRESCALER_32 ŸÚ P WWDT_PRESCALER_64 šÚ P WWDT_PRESCALER_128 gÚ P WWDT_PRESCALER_192 fÚ P WWDT_PRESCALER_256 eÚ P WWDT_PRESCALER_384 cÚ P WWDT_PRESCALER_512 jÚ P WWDT_PRESCALER_768 ]Ú P WWDT_PRESCALER_1024 9Ú P WWDT_PRESCALER_1536 1Ú P WWDT_PRESCALER_2048 2Ú P WWDT_RELOAD_WORD ´Ú P WWDT_CLEAR_RESET_FLAG :Ú P WWDT_CLEAR_INT_FLAG ÖÚ P WWDT_GET_RESET_FLAG ÅÚ P WWDT_GET_INT_FLAG aÚ P WWDT_GET_COUNTER §Ú P WWDT_RELOAD_COUNTER ÊÚ ,
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u32PreScale àÚ ,
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u32CmpValue ÒÚ ,
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u32EnableInt {Ú
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WWDT_Open ŸÚ
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bsp_led_init äÚ , dat §Ú bsp_led_set NÚ , dat §Ú bsp_led_blink †Ú P bsp_led_io2 sÚ P bsp_led_io1 tÚ P C_LED_ON HÚ P
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C_LED_OFF Ú ," „ dat äÚ " „ temp ‰Ú ," † dat âÛ
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€ cÛJ
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