; generated by Component: ARM Compiler 5.06 update 4 (build 422) Tool: ArmCC [4d3604]
; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o.\obj\pwm.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\pwm.d --cpu=Cortex-M0 --apcs=interwork -O3 --diag_suppress=9931 -I..\..\..\Library\CMSIS\Include -I..\..\..\Library\Device\Nuvoton\Mini58Series\Include -I..\..\..\Library\StdDriver\inc -I..\..\Template -I..\..\..\Library\StdDriver\driver -I.\RTE\_Template -ID:\Keil_v5\ARM\PACK\Nuvoton\NuMicro_DFP\1.0.9\Device\Mini58\Include -ID:\Keil_v5\ARM\CMSIS\Include -D__MICROLIB -D__UVISION_VERSION=523 --omf_browse=.\obj\pwm.crf ..\..\..\Library\StdDriver\src\pwm.c]
                          THUMB

                          AREA ||i.PWM_ClearADCTriggerFlag||, CODE, READONLY, ALIGN=2

                  PWM_ClearADCTriggerFlag PROC
;;;211     */
;;;212    void PWM_ClearADCTriggerFlag (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
000000  4807              LDR      r0,|L1.32|
;;;213    {
;;;214        if(u32ChannelNum < 4) {
;;;215            PWM->ADCTSTS0 |= (u32Condition << (8 * u32ChannelNum));
000002  00cb              LSLS     r3,r1,#3
000004  2904              CMP      r1,#4                 ;214
000006  d204              BCS      |L1.18|
000008  6b01              LDR      r1,[r0,#0x30]
00000a  409a              LSLS     r2,r2,r3
00000c  4311              ORRS     r1,r1,r2
00000e  6301              STR      r1,[r0,#0x30]
;;;216        } else {
;;;217            PWM->ADCTSTS1 |= (u32Condition << (8 * (u32ChannelNum - 4)));
;;;218        }
;;;219    }
000010  4770              BX       lr
                  |L1.18|
000012  3b20              SUBS     r3,r3,#0x20
000014  6b41              LDR      r1,[r0,#0x34]         ;217
000016  409a              LSLS     r2,r2,r3              ;217
000018  430a              ORRS     r2,r2,r1              ;217
00001a  6342              STR      r2,[r0,#0x34]         ;217
00001c  4770              BX       lr
;;;220    
                          ENDP

00001e  0000              DCW      0x0000
                  |L1.32|
                          DCD      0x40040040

                          AREA ||i.PWM_ClearCenterIntFlag||, CODE, READONLY, ALIGN=2

                  PWM_ClearCenterIntFlag PROC
;;;547     */
;;;548    void PWM_ClearCenterIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
000000  2001              MOVS     r0,#1
;;;549    {
;;;550        PWM->INTSTS = (PWM_INTSTS_PIF0_Msk << u32ChannelNum);
000002  0480              LSLS     r0,r0,#18
000004  4088              LSLS     r0,r0,r1
000006  4901              LDR      r1,|L2.12|
000008  6188              STR      r0,[r1,#0x18]
;;;551    }
00000a  4770              BX       lr
;;;552    
                          ENDP

                  |L2.12|
                          DCD      0x40040040

                          AREA ||i.PWM_ClearDutyIntFlag||, CODE, READONLY, ALIGN=2

                  PWM_ClearDutyIntFlag PROC
;;;355     */
;;;356    void PWM_ClearDutyIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
000000  20ff              MOVS     r0,#0xff
;;;357    {
;;;358        PWM->INTSTS = (PWM_INTSTS_CMPDIF0_Msk << u32ChannelNum);
000002  3001              ADDS     r0,#1
000004  4088              LSLS     r0,r0,r1
000006  4901              LDR      r1,|L3.12|
000008  6188              STR      r0,[r1,#0x18]
;;;359    }
00000a  4770              BX       lr
;;;360    
                          ENDP

                  |L3.12|
                          DCD      0x40040040

                          AREA ||i.PWM_ClearFaultBrakeFlag||, CODE, READONLY, ALIGN=2

                  PWM_ClearFaultBrakeFlag PROC
;;;265     */
;;;266    void PWM_ClearFaultBrakeFlag (PWM_T *pwm, uint32_t u32BrakeSource)
000000  4901              LDR      r1,|L4.8|
;;;267    {
;;;268        PWM->BRKCTL = PWM_BRKCTL_BRKSTS_Msk;
000002  2080              MOVS     r0,#0x80
000004  6208              STR      r0,[r1,#0x20]
;;;269    }
000006  4770              BX       lr
;;;270    
                          ENDP

                  |L4.8|
                          DCD      0x40040040

                          AREA ||i.PWM_ClearFaultBrakeIntFlag||, CODE, READONLY, ALIGN=2

                  PWM_ClearFaultBrakeIntFlag PROC
;;;495     */
;;;496    void PWM_ClearFaultBrakeIntFlag (PWM_T *pwm, uint32_t u32BrakeSource)
000000  4801              LDR      r0,|L5.8|
;;;497    {
;;;498        PWM->INTSTS = u32BrakeSource;
000002  6181              STR      r1,[r0,#0x18]
;;;499    }
000004  4770              BX       lr
;;;500    
                          ENDP

000006  0000              DCW      0x0000
                  |L5.8|
                          DCD      0x40040040

                          AREA ||i.PWM_ClearPeriodIntFlag||, CODE, READONLY, ALIGN=2

                  PWM_ClearPeriodIntFlag PROC
;;;401     */
;;;402    void PWM_ClearPeriodIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
000000  2001              MOVS     r0,#1
;;;403    {
;;;404        PWM->INTSTS = (PWM_INTSTS_ZIF0_Msk << u32ChannelNum);
000002  4088              LSLS     r0,r0,r1
000004  4901              LDR      r1,|L6.12|
000006  6188              STR      r0,[r1,#0x18]
;;;405    }
000008  4770              BX       lr
;;;406    
                          ENDP

00000a  0000              DCW      0x0000
                  |L6.12|
                          DCD      0x40040040

                          AREA ||i.PWM_ClearRiseIntFlag||, CODE, READONLY, ALIGN=2

                  PWM_ClearRiseIntFlag PROC
;;;447     */
;;;448    void PWM_ClearRiseIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
000000  2001              MOVS     r0,#1
;;;449    {
;;;450        PWM->INTSTS = (PWM_INTSTS_CMPUIF0_Msk << u32ChannelNum);
000002  0600              LSLS     r0,r0,#24
000004  4088              LSLS     r0,r0,r1
000006  4901              LDR      r1,|L7.12|
000008  6188              STR      r0,[r1,#0x18]
;;;451    }
00000a  4770              BX       lr
;;;452    
                          ENDP

                  |L7.12|
                          DCD      0x40040040

                          AREA ||i.PWM_ConfigOutputChannel||, CODE, READONLY, ALIGN=2

                  PWM_ConfigOutputChannel PROC
;;;35      */
;;;36     uint32_t PWM_ConfigOutputChannel (PWM_T *pwm,
000000  b5ff              PUSH     {r0-r7,lr}
;;;37                                       uint32_t u32ChannelNum,
;;;38                                       uint32_t u32Frequency,
;;;39                                       uint32_t u32DutyCycle)
;;;40     {
;;;41         uint32_t i = SystemCoreClock / u32Frequency;
000002  4839              LDR      r0,|L8.232|
000004  b083              SUB      sp,sp,#0xc            ;40
000006  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
000008  461c              MOV      r4,r3                 ;40
00000a  4611              MOV      r1,r2
00000c  9001              STR      r0,[sp,#4]
00000e  f7fffffe          BL       __aeabi_uidivmod
;;;42         uint8_t  u8Divider = 1, u8Prescale = 0xFF;
000012  2601              MOVS     r6,#1
;;;43         uint16_t u16CNR = 0xFFFF;
000014  4d35              LDR      r5,|L8.236|
000016  27ff              MOVS     r7,#0xff              ;42
000018  9000              STR      r0,[sp,#0]
                  |L8.26|
;;;44     
;;;45         for(; u8Divider < 17; u8Divider <<= 1) {  // clk divider could only be 1, 2, 4, 8, 16
;;;46             i = (SystemCoreClock / u32Frequency) / u8Divider;
00001a  4631              MOV      r1,r6
00001c  9800              LDR      r0,[sp,#0]
00001e  f7fffffe          BL       __aeabi_uidivmod
;;;47             // If target value is larger than CNR * prescale, need to use a larger divider
;;;48             if(i > (0x10000 * 0x100))
000022  2101              MOVS     r1,#1
000024  0609              LSLS     r1,r1,#24
000026  4288              CMP      r0,r1
000028  d812              BHI      |L8.80|
;;;49                 continue;
;;;50     
;;;51             // CNR = 0xFFFF + 1, get a prescaler that CNR value is below 0xFFFF
;;;52             u8Prescale = (i + 0xFFFF)/ 0x10000;
00002a  1941              ADDS     r1,r0,r5
00002c  0209              LSLS     r1,r1,#8
00002e  0e0f              LSRS     r7,r1,#24
;;;53     
;;;54             // u8Prescale must at least be 2, otherwise the output stop
;;;55             if(u8Prescale < 3)
000030  2f03              CMP      r7,#3
000032  d200              BCS      |L8.54|
;;;56                 u8Prescale = 2;
000034  2702              MOVS     r7,#2
                  |L8.54|
;;;57     
;;;58             i /= u8Prescale;
000036  4639              MOV      r1,r7
000038  f7fffffe          BL       __aeabi_uidivmod
;;;59     
;;;60             if(i <= 0x10000) {
00003c  2101              MOVS     r1,#1
00003e  0409              LSLS     r1,r1,#16
000040  4288              CMP      r0,r1
000042  d805              BHI      |L8.80|
;;;61                 if(i == 1)
000044  2801              CMP      r0,#1
000046  d001              BEQ      |L8.76|
;;;62                     u16CNR = 1;     // Too fast, and PWM cannot generate expected frequency...
;;;63                 else
;;;64                     u16CNR = i;
000048  b285              UXTH     r5,r0
00004a  e005              B        |L8.88|
                  |L8.76|
00004c  2501              MOVS     r5,#1                 ;62
00004e  e003              B        |L8.88|
                  |L8.80|
000050  0670              LSLS     r0,r6,#25             ;45
000052  0e06              LSRS     r6,r0,#24             ;45
000054  2e11              CMP      r6,#0x11              ;45
000056  d3e0              BCC      |L8.26|
                  |L8.88|
;;;65                 break;
;;;66             }
;;;67     
;;;68         }
;;;69         // Store return value here 'cos we're gonna change u8Divider & u8Prescale & u16CNR to the real value to fill into register
;;;70         i = SystemCoreClock / (u8Prescale * u8Divider * u16CNR);
000058  4639              MOV      r1,r7
00005a  4371              MULS     r1,r6,r1
00005c  4369              MULS     r1,r5,r1
00005e  9801              LDR      r0,[sp,#4]
000060  f7fffffe          BL       __aeabi_uidivmod
000064  1e7f              SUBS     r7,r7,#1
;;;71     
;;;72         u8Prescale -= 1;
000066  1e6d              SUBS     r5,r5,#1
000068  b2ff              UXTB     r7,r7
;;;73         u16CNR -= 1;
00006a  b2ad              UXTH     r5,r5
;;;74         // convert to real register value
;;;75         if(u8Divider == 1)
00006c  9000              STR      r0,[sp,#0]
00006e  2e01              CMP      r6,#1
000070  d030              BEQ      |L8.212|
;;;76             u8Divider = 4;
;;;77         else if (u8Divider == 2)
000072  2e02              CMP      r6,#2
000074  d030              BEQ      |L8.216|
;;;78             u8Divider = 0;
;;;79         else if (u8Divider == 4)
000076  2e04              CMP      r6,#4
000078  d030              BEQ      |L8.220|
;;;80             u8Divider = 1;
;;;81         else if (u8Divider == 8)
00007a  2e08              CMP      r6,#8
00007c  d030              BEQ      |L8.224|
;;;82             u8Divider = 2;
;;;83         else // 16
;;;84             u8Divider = 3;
00007e  2103              MOVS     r1,#3
                  |L8.128|
;;;85     
;;;86         // every two channels share a prescaler
;;;87         PWM->CLKPSC = (PWM->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << ((u32ChannelNum >> 1) * 8))) | (u8Prescale << ((u32ChannelNum >> 1) * 8));
000080  481b              LDR      r0,|L8.240|
000082  6802              LDR      r2,[r0,#0]
000084  9b04              LDR      r3,[sp,#0x10]
000086  26ff              MOVS     r6,#0xff
000088  085b              LSRS     r3,r3,#1
00008a  00db              LSLS     r3,r3,#3
00008c  409e              LSLS     r6,r6,r3
00008e  43b2              BICS     r2,r2,r6
000090  409f              LSLS     r7,r7,r3
000092  433a              ORRS     r2,r2,r7
000094  6002              STR      r2,[r0,#0]
;;;88         PWM->CLKDIV = (PWM->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << (4 * u32ChannelNum))) | (u8Divider << (4 * u32ChannelNum));
000096  6843              LDR      r3,[r0,#4]
000098  9a04              LDR      r2,[sp,#0x10]
00009a  2607              MOVS     r6,#7
00009c  0092              LSLS     r2,r2,#2
00009e  4096              LSLS     r6,r6,r2
0000a0  43b3              BICS     r3,r3,r6
0000a2  4091              LSLS     r1,r1,r2
0000a4  430b              ORRS     r3,r3,r1
0000a6  6043              STR      r3,[r0,#4]
;;;89         PWM->CTL = (PWM->CTL & ~PWM_CTL_CNTTYPE_Msk) | (PWM_CTL_CNTMODE0_Msk << ((4 * u32ChannelNum)));
0000a8  6881              LDR      r1,[r0,#8]
0000aa  2308              MOVS     r3,#8
0000ac  0049              LSLS     r1,r1,#1
0000ae  0849              LSRS     r1,r1,#1
0000b0  4093              LSLS     r3,r3,r2
0000b2  4319              ORRS     r1,r1,r3
0000b4  6081              STR      r1,[r0,#8]
;;;90     
;;;91         if(u32DutyCycle == 0)
;;;92             *((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + u32ChannelNum * 4))) = 0;
0000b6  9803              LDR      r0,[sp,#0xc]
0000b8  1816              ADDS     r6,r2,r0
0000ba  2c00              CMP      r4,#0                 ;91
0000bc  d012              BEQ      |L8.228|
;;;93         else
;;;94             *((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + u32ChannelNum * 4))) = u32DutyCycle * (u16CNR + 1) / 100 - 1;
0000be  1c68              ADDS     r0,r5,#1
0000c0  4360              MULS     r0,r4,r0
0000c2  2164              MOVS     r1,#0x64
0000c4  f7fffffe          BL       __aeabi_uidivmod
0000c8  1e40              SUBS     r0,r0,#1
                  |L8.202|
0000ca  6270              STR      r0,[r6,#0x24]
;;;95     
;;;96         *((__IO uint32_t *)((((uint32_t) & ((pwm)->PERIOD0)) + (u32ChannelNum) * 4))) = u16CNR;
0000cc  60f5              STR      r5,[r6,#0xc]
;;;97     
;;;98         return(i);
0000ce  9800              LDR      r0,[sp,#0]
;;;99     }
0000d0  b007              ADD      sp,sp,#0x1c
0000d2  bdf0              POP      {r4-r7,pc}
                  |L8.212|
0000d4  2104              MOVS     r1,#4                 ;76
0000d6  e7d3              B        |L8.128|
                  |L8.216|
0000d8  2100              MOVS     r1,#0                 ;78
0000da  e7d1              B        |L8.128|
                  |L8.220|
0000dc  2101              MOVS     r1,#1                 ;80
0000de  e7cf              B        |L8.128|
                  |L8.224|
0000e0  2102              MOVS     r1,#2                 ;82
0000e2  e7cd              B        |L8.128|
                  |L8.228|
0000e4  2000              MOVS     r0,#0                 ;92
0000e6  e7f0              B        |L8.202|
;;;100    
                          ENDP

                  |L8.232|
                          DCD      SystemCoreClock
                  |L8.236|
                          DCD      0x0000ffff
                  |L8.240|
                          DCD      0x40040000

                          AREA ||i.PWM_DisableADCTrigger||, CODE, READONLY, ALIGN=2

                  PWM_DisableADCTrigger PROC
;;;189     */
;;;190    void PWM_DisableADCTrigger (PWM_T *pwm, uint32_t u32ChannelNum)
000000  4b07              LDR      r3,|L9.32|
;;;191    {
;;;192        if(u32ChannelNum < 4) {
;;;193            PWM->ADCTCTL0 = (PWM->ADCTCTL0 & ~((PWM_TRIGGER_ADC_CNTR_IS_0 |
000002  00ca              LSLS     r2,r1,#3
000004  200f              MOVS     r0,#0xf
000006  2904              CMP      r1,#4                 ;192
000008  d204              BCS      |L9.20|
00000a  6a99              LDR      r1,[r3,#0x28]
00000c  4090              LSLS     r0,r0,r2
00000e  4381              BICS     r1,r1,r0
000010  6299              STR      r1,[r3,#0x28]
;;;194                                                PWM_TRIGGER_ADC_CNTR_IS_CMR_D |
;;;195                                                PWM_TRIGGER_ADC_CNTR_IS_CNR |
;;;196                                                PWM_TRIGGER_ADC_CNTR_IS_CMR_U ) << (8 * u32ChannelNum)));
;;;197        } else {
;;;198            PWM->ADCTCTL1 = (PWM->ADCTCTL1 & ~((PWM_TRIGGER_ADC_CNTR_IS_0 |
;;;199                                                PWM_TRIGGER_ADC_CNTR_IS_CMR_D |
;;;200                                                PWM_TRIGGER_ADC_CNTR_IS_CNR |
;;;201                                                PWM_TRIGGER_ADC_CNTR_IS_CMR_U ) << (8 * (u32ChannelNum - 4))));
;;;202        }
;;;203    }
000012  4770              BX       lr
                  |L9.20|
000014  3a20              SUBS     r2,r2,#0x20
000016  6ad9              LDR      r1,[r3,#0x2c]         ;198
000018  4090              LSLS     r0,r0,r2              ;198
00001a  4381              BICS     r1,r1,r0              ;198
00001c  62d9              STR      r1,[r3,#0x2c]         ;198
00001e  4770              BX       lr
;;;204    
                          ENDP

                  |L9.32|
                          DCD      0x40040040

                          AREA ||i.PWM_DisableCenterInt||, CODE, READONLY, ALIGN=2

                  PWM_DisableCenterInt PROC
;;;536     */
;;;537    void PWM_DisableCenterInt (PWM_T *pwm, uint32_t u32ChannelNum)
000000  4803              LDR      r0,|L10.16|
;;;538    {
;;;539        PWM->INTEN &= ~(PWM_INTEN_PIEN0_Msk << u32ChannelNum);
000002  6942              LDR      r2,[r0,#0x14]
000004  2301              MOVS     r3,#1
000006  049b              LSLS     r3,r3,#18
000008  408b              LSLS     r3,r3,r1
00000a  439a              BICS     r2,r2,r3
00000c  6142              STR      r2,[r0,#0x14]
;;;540    }
00000e  4770              BX       lr
;;;541    
                          ENDP

                  |L10.16|
                          DCD      0x40040040

                          AREA ||i.PWM_DisableDeadZone||, CODE, READONLY, ALIGN=2

                  PWM_DisableDeadZone PROC
;;;318     */
;;;319    void PWM_DisableDeadZone (PWM_T *pwm, uint32_t u32ChannelNum)
000000  4803              LDR      r0,|L11.16|
;;;320    {
;;;321        // every two channels shares the same setting
;;;322        u32ChannelNum >>= 1;
000002  0849              LSRS     r1,r1,#1
;;;323        // enable dead zone
;;;324        PWM->CTL &= ~(PWM_CTL_DTCNT01_Msk << u32ChannelNum);
000004  6882              LDR      r2,[r0,#8]
000006  0183              LSLS     r3,r0,#6
000008  408b              LSLS     r3,r3,r1
00000a  439a              BICS     r2,r2,r3
00000c  6082              STR      r2,[r0,#8]
;;;325    }
00000e  4770              BX       lr
;;;326    
                          ENDP

                  |L11.16|
                          DCD      0x40040000

                          AREA ||i.PWM_DisableDutyInt||, CODE, READONLY, ALIGN=1

                  PWM_DisableDutyInt PROC
;;;344     */
;;;345    void PWM_DisableDutyInt (PWM_T *pwm, uint32_t u32ChannelNum)
000000  6d42              LDR      r2,[r0,#0x54]
;;;346    {
;;;347        (pwm)->INTEN &= ~((1 << PWM_INTEN_CMPDIEN0_Pos) << u32ChannelNum);
000002  23ff              MOVS     r3,#0xff
000004  3301              ADDS     r3,#1
000006  408b              LSLS     r3,r3,r1
000008  439a              BICS     r2,r2,r3
00000a  6542              STR      r2,[r0,#0x54]
;;;348    }
00000c  4770              BX       lr
;;;349    
                          ENDP


                          AREA ||i.PWM_DisableFaultBrakeInt||, CODE, READONLY, ALIGN=2

                  PWM_DisableFaultBrakeInt PROC
;;;482     */
;;;483    void PWM_DisableFaultBrakeInt (PWM_T *pwm, uint32_t u32BrakeSource)
000000  4803              LDR      r0,|L13.16|
;;;484    {
;;;485        PWM->INTEN &= ~PWM_INTEN_BRKIEN_Msk;
000002  6941              LDR      r1,[r0,#0x14]
000004  2201              MOVS     r2,#1
000006  0412              LSLS     r2,r2,#16
000008  4391              BICS     r1,r1,r2
00000a  6141              STR      r1,[r0,#0x14]
;;;486    }
00000c  4770              BX       lr
;;;487    
                          ENDP

00000e  0000              DCW      0x0000
                  |L13.16|
                          DCD      0x40040040

                          AREA ||i.PWM_DisableOutput||, CODE, READONLY, ALIGN=2

                  PWM_DisableOutput PROC
;;;289     */
;;;290    void PWM_DisableOutput (PWM_T *pwm, uint32_t u32ChannelMask)
000000  4802              LDR      r0,|L14.12|
;;;291    {
;;;292        PWM->POEN &= ~u32ChannelMask;
000002  69c2              LDR      r2,[r0,#0x1c]
000004  438a              BICS     r2,r2,r1
000006  61c2              STR      r2,[r0,#0x1c]
;;;293    }
000008  4770              BX       lr
;;;294    
                          ENDP

00000a  0000              DCW      0x0000
                  |L14.12|
                          DCD      0x40040040

                          AREA ||i.PWM_DisablePeriodInt||, CODE, READONLY, ALIGN=1

                  PWM_DisablePeriodInt PROC
;;;390     */
;;;391    void PWM_DisablePeriodInt (PWM_T *pwm, uint32_t u32ChannelNum)
000000  6d42              LDR      r2,[r0,#0x54]
;;;392    {
;;;393        (pwm)->INTEN &= ~((1 << PWM_INTEN_ZIEN0_Pos) << u32ChannelNum);
000002  2301              MOVS     r3,#1
000004  408b              LSLS     r3,r3,r1
000006  439a              BICS     r2,r2,r3
000008  6542              STR      r2,[r0,#0x54]
;;;394    }
00000a  4770              BX       lr
;;;395    
                          ENDP


                          AREA ||i.PWM_DisableRiseInt||, CODE, READONLY, ALIGN=1

                  PWM_DisableRiseInt PROC
;;;436     */
;;;437    void PWM_DisableRiseInt (PWM_T *pwm, uint32_t u32ChannelNum)
000000  6d42              LDR      r2,[r0,#0x54]
;;;438    {
;;;439        (pwm)->INTEN &= ~((1 << PWM_INTEN_CMPUIEN0_Pos) << u32ChannelNum);
000002  2301              MOVS     r3,#1
000004  061b              LSLS     r3,r3,#24
000006  408b              LSLS     r3,r3,r1
000008  439a              BICS     r2,r2,r3
00000a  6542              STR      r2,[r0,#0x54]
;;;440    }
00000c  4770              BX       lr
;;;441    
                          ENDP


                          AREA ||i.PWM_EnableADCTrigger||, CODE, READONLY, ALIGN=2

                  PWM_EnableADCTrigger PROC
;;;168     */
;;;169    void PWM_EnableADCTrigger (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
000000  b510              PUSH     {r4,lr}
;;;170    {
;;;171        if(u32ChannelNum < 4) {
;;;172            PWM->ADCTCTL0 = (PWM->ADCTCTL0 & ~((PWM_TRIGGER_ADC_CNTR_IS_0 |
000002  4b0a              LDR      r3,|L17.44|
000004  240f              MOVS     r4,#0xf
000006  00c8              LSLS     r0,r1,#3
000008  2904              CMP      r1,#4                 ;171
00000a  d206              BCS      |L17.26|
00000c  6a99              LDR      r1,[r3,#0x28]
00000e  4084              LSLS     r4,r4,r0
000010  43a1              BICS     r1,r1,r4
000012  4082              LSLS     r2,r2,r0
000014  4311              ORRS     r1,r1,r2
000016  6299              STR      r1,[r3,#0x28]
;;;173                                                PWM_TRIGGER_ADC_CNTR_IS_CMR_D |
;;;174                                                PWM_TRIGGER_ADC_CNTR_IS_CNR |
;;;175                                                PWM_TRIGGER_ADC_CNTR_IS_CMR_U ) << (8 * u32ChannelNum))) | (u32Condition << (8 * u32ChannelNum));
;;;176        } else {
;;;177            PWM->ADCTCTL1 = (PWM->ADCTCTL1 & ~((PWM_TRIGGER_ADC_CNTR_IS_0 |
;;;178                                                PWM_TRIGGER_ADC_CNTR_IS_CMR_D |
;;;179                                                PWM_TRIGGER_ADC_CNTR_IS_CNR |
;;;180                                                PWM_TRIGGER_ADC_CNTR_IS_CMR_U ) << (8 * (u32ChannelNum - 4)))) | (u32Condition << (8 * (u32ChannelNum - 4)));
;;;181        }
;;;182    }
000018  bd10              POP      {r4,pc}
                  |L17.26|
00001a  3820              SUBS     r0,r0,#0x20
00001c  6ad9              LDR      r1,[r3,#0x2c]         ;177
00001e  4084              LSLS     r4,r4,r0              ;177
000020  43a1              BICS     r1,r1,r4              ;177
000022  4082              LSLS     r2,r2,r0              ;177
000024  4311              ORRS     r1,r1,r2              ;177
000026  62d9              STR      r1,[r3,#0x2c]         ;177
000028  bd10              POP      {r4,pc}
;;;183    
                          ENDP

00002a  0000              DCW      0x0000
                  |L17.44|
                          DCD      0x40040040

                          AREA ||i.PWM_EnableCenterInt||, CODE, READONLY, ALIGN=2

                  PWM_EnableCenterInt PROC
;;;525     */
;;;526    void PWM_EnableCenterInt (PWM_T *pwm, uint32_t u32ChannelNum,  uint32_t u32IntPeriodType)
000000  b510              PUSH     {r4,lr}
;;;527    {
;;;528        PWM->INTEN = (PWM->INTEN & ~PWM_INTEN_PINTTYPE_Msk & ~(PWM_INTEN_PIEN0_Msk << u32ChannelNum)) | (PWM_INTEN_PIEN0_Msk << u32ChannelNum) | u32IntPeriodType;
000002  4c06              LDR      r4,|L18.28|
000004  6963              LDR      r3,[r4,#0x14]
000006  2001              MOVS     r0,#1
000008  0480              LSLS     r0,r0,#18
00000a  4088              LSLS     r0,r0,r1
00000c  4904              LDR      r1,|L18.32|
00000e  4381              BICS     r1,r1,r0
000010  400b              ANDS     r3,r3,r1
000012  4303              ORRS     r3,r3,r0
000014  4313              ORRS     r3,r3,r2
000016  6163              STR      r3,[r4,#0x14]
;;;529    }
000018  bd10              POP      {r4,pc}
;;;530    
                          ENDP

00001a  0000              DCW      0x0000
                  |L18.28|
                          DCD      0x40040040
                  |L18.32|
                          DCD      0xfffdffff

                          AREA ||i.PWM_EnableDeadZone||, CODE, READONLY, ALIGN=2

                  PWM_EnableDeadZone PROC
;;;302     */
;;;303    void PWM_EnableDeadZone (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration)
000000  b530              PUSH     {r4,r5,lr}
;;;304    {
;;;305        // every two channels shares the same setting
;;;306        u32ChannelNum >>= 1;
;;;307        // set duration
;;;308        PWM->DTCTL = (PWM->DTCTL & ~(PWM_DTCTL_DTI01_Msk << (8 * u32ChannelNum))) | (u32Duration << (8 * u32ChannelNum));
000002  4b08              LDR      r3,|L19.36|
000004  0848              LSRS     r0,r1,#1              ;306
000006  6a59              LDR      r1,[r3,#0x24]
000008  00c4              LSLS     r4,r0,#3
00000a  25ff              MOVS     r5,#0xff
00000c  40a5              LSLS     r5,r5,r4
00000e  43a9              BICS     r1,r1,r5
000010  40a2              LSLS     r2,r2,r4
000012  4311              ORRS     r1,r1,r2
000014  6259              STR      r1,[r3,#0x24]
;;;309        // enable dead zone
;;;310        PWM->CTL |= (PWM_CTL_DTCNT01_Msk << u32ChannelNum);
000016  0319              LSLS     r1,r3,#12
000018  688a              LDR      r2,[r1,#8]
00001a  018b              LSLS     r3,r1,#6
00001c  4083              LSLS     r3,r3,r0
00001e  431a              ORRS     r2,r2,r3
000020  608a              STR      r2,[r1,#8]
;;;311    }
000022  bd30              POP      {r4,r5,pc}
;;;312    
                          ENDP

                  |L19.36|
                          DCD      0x40040040

                          AREA ||i.PWM_EnableDutyInt||, CODE, READONLY, ALIGN=1

                  PWM_EnableDutyInt PROC
;;;333     */
;;;334    void PWM_EnableDutyInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
000000  6d42              LDR      r2,[r0,#0x54]
;;;335    {
;;;336        (pwm)->INTEN |= ((1 << PWM_INTEN_CMPDIEN0_Pos) << u32ChannelNum);
000002  23ff              MOVS     r3,#0xff
000004  3301              ADDS     r3,#1
000006  408b              LSLS     r3,r3,r1
000008  431a              ORRS     r2,r2,r3
00000a  6542              STR      r2,[r0,#0x54]
;;;337    }
00000c  4770              BX       lr
;;;338    
                          ENDP


                          AREA ||i.PWM_EnableFaultBrake||, CODE, READONLY, ALIGN=2

                  PWM_EnableFaultBrake PROC
;;;250     */
;;;251    void PWM_EnableFaultBrake (PWM_T *pwm,
000000  0610              LSLS     r0,r2,#24
;;;252                               uint32_t u32ChannelMask,
;;;253                               uint32_t u32LevelMask,
;;;254                               uint32_t u32BrakeSource)
;;;255    {
;;;256        PWM->BRKCTL = (u32LevelMask << PWM_BRKCTL_BKOD0_Pos) | u32BrakeSource;
000002  4902              LDR      r1,|L21.12|
000004  4318              ORRS     r0,r0,r3
000006  6208              STR      r0,[r1,#0x20]
;;;257    }
000008  4770              BX       lr
;;;258    
                          ENDP

00000a  0000              DCW      0x0000
                  |L21.12|
                          DCD      0x40040040

                          AREA ||i.PWM_EnableFaultBrakeInt||, CODE, READONLY, ALIGN=2

                  PWM_EnableFaultBrakeInt PROC
;;;471     */
;;;472    void PWM_EnableFaultBrakeInt (PWM_T *pwm, uint32_t u32BrakeSource)
000000  4803              LDR      r0,|L22.16|
;;;473    {
;;;474        PWM->INTEN |= PWM_INTEN_BRKIEN_Msk;
000002  6941              LDR      r1,[r0,#0x14]
000004  2201              MOVS     r2,#1
000006  0412              LSLS     r2,r2,#16
000008  4311              ORRS     r1,r1,r2
00000a  6141              STR      r1,[r0,#0x14]
;;;475    }
00000c  4770              BX       lr
;;;476    
                          ENDP

00000e  0000              DCW      0x0000
                  |L22.16|
                          DCD      0x40040040

                          AREA ||i.PWM_EnableOutput||, CODE, READONLY, ALIGN=2

                  PWM_EnableOutput PROC
;;;277     */
;;;278    void PWM_EnableOutput (PWM_T *pwm, uint32_t u32ChannelMask)
000000  4802              LDR      r0,|L23.12|
;;;279    {
;;;280        PWM->POEN |= u32ChannelMask;
000002  69c2              LDR      r2,[r0,#0x1c]
000004  430a              ORRS     r2,r2,r1
000006  61c2              STR      r2,[r0,#0x1c]
;;;281    }
000008  4770              BX       lr
;;;282    
                          ENDP

00000a  0000              DCW      0x0000
                  |L23.12|
                          DCD      0x40040040

                          AREA ||i.PWM_EnablePeriodInt||, CODE, READONLY, ALIGN=1

                  PWM_EnablePeriodInt PROC
;;;379     */
;;;380    void PWM_EnablePeriodInt (PWM_T *pwm, uint32_t u32ChannelNum)
000000  6d42              LDR      r2,[r0,#0x54]
;;;381    {
;;;382        (pwm)->INTEN |= ((1 << PWM_INTEN_ZIEN0_Pos) << u32ChannelNum);
000002  2301              MOVS     r3,#1
000004  408b              LSLS     r3,r3,r1
000006  431a              ORRS     r2,r2,r3
000008  6542              STR      r2,[r0,#0x54]
;;;383    }
00000a  4770              BX       lr
;;;384    
                          ENDP


                          AREA ||i.PWM_EnableRiseInt||, CODE, READONLY, ALIGN=1

                  PWM_EnableRiseInt PROC
;;;425     */
;;;426    void PWM_EnableRiseInt (PWM_T *pwm, uint32_t u32ChannelNum)
000000  6d42              LDR      r2,[r0,#0x54]
;;;427    {
;;;428        (pwm)->INTEN |= ((1 << PWM_INTEN_CMPUIEN0_Pos) << u32ChannelNum);
000002  2301              MOVS     r3,#1
000004  061b              LSLS     r3,r3,#24
000006  408b              LSLS     r3,r3,r1
000008  431a              ORRS     r2,r2,r3
00000a  6542              STR      r2,[r0,#0x54]
;;;429    }
00000c  4770              BX       lr
;;;430    
                          ENDP


                          AREA ||i.PWM_ForceStop||, CODE, READONLY, ALIGN=2

                  PWM_ForceStop PROC
;;;145     */
;;;146    void PWM_ForceStop (PWM_T *pwm, uint32_t u32ChannelMask)
000000  b530              PUSH     {r4,r5,lr}
;;;147    {
;;;148        uint32_t u32Mask = 0, i;
000002  2300              MOVS     r3,#0
;;;149        for(i = 0; i < PWM_CHANNEL_NUM; i ++) {
000004  461a              MOV      r2,r3
;;;150            if(u32ChannelMask & (1 << i)) {
000006  2001              MOVS     r0,#1
                  |L26.8|
000008  4604              MOV      r4,r0
00000a  4094              LSLS     r4,r4,r2
00000c  420c              TST      r4,r1
00000e  d003              BEQ      |L26.24|
000010  0095              LSLS     r5,r2,#2
000012  4604              MOV      r4,r0
;;;151                u32Mask |= (PWM_CTL_CNTEN0_Msk << (i * 4));
000014  40ac              LSLS     r4,r4,r5
000016  4323              ORRS     r3,r3,r4
                  |L26.24|
000018  1c52              ADDS     r2,r2,#1
00001a  2a06              CMP      r2,#6                 ;149
00001c  d3f4              BCC      |L26.8|
;;;152            }
;;;153        }
;;;154    
;;;155        PWM->CTL &= ~u32Mask;
00001e  4802              LDR      r0,|L26.40|
000020  6881              LDR      r1,[r0,#8]
000022  4399              BICS     r1,r1,r3
000024  6081              STR      r1,[r0,#8]
;;;156    }
000026  bd30              POP      {r4,r5,pc}
;;;157    
                          ENDP

                  |L26.40|
                          DCD      0x40040000

                          AREA ||i.PWM_GetADCTriggerFlag||, CODE, READONLY, ALIGN=2

                  PWM_GetADCTriggerFlag PROC
;;;227     */
;;;228    uint32_t PWM_GetADCTriggerFlag (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
000000  4b08              LDR      r3,|L27.36|
;;;229    {
;;;230        if(u32ChannelNum < 4) {
;;;231            return(PWM->ADCTSTS0 & (u32Condition << (8 * u32ChannelNum)) ? 1 : 0);
000002  00c8              LSLS     r0,r1,#3
000004  2904              CMP      r1,#4                 ;230
000006  d204              BCS      |L27.18|
000008  6b19              LDR      r1,[r3,#0x30]
00000a  4082              LSLS     r2,r2,r0
00000c  4211              TST      r1,r2
00000e  d105              BNE      |L27.28|
000010  e006              B        |L27.32|
                  |L27.18|
000012  3820              SUBS     r0,r0,#0x20
;;;232        } else {
;;;233            return(PWM->ADCTSTS1 & (u32Condition << (8 * (u32ChannelNum - 4))) ? 1 : 0);
000014  4082              LSLS     r2,r2,r0
000016  6b58              LDR      r0,[r3,#0x34]
000018  4202              TST      r2,r0
00001a  d001              BEQ      |L27.32|
                  |L27.28|
00001c  2001              MOVS     r0,#1
;;;234        }
;;;235    }
00001e  4770              BX       lr
                  |L27.32|
000020  2000              MOVS     r0,#0                 ;233
000022  4770              BX       lr
;;;236    
                          ENDP

                  |L27.36|
                          DCD      0x40040040

                          AREA ||i.PWM_GetCenterIntFlag||, CODE, READONLY, ALIGN=2

                  PWM_GetCenterIntFlag PROC
;;;560     */
;;;561    uint32_t PWM_GetCenterIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
000000  4804              LDR      r0,|L28.20|
;;;562    {
;;;563        return(PWM->INTSTS & (PWM_INTSTS_PIF0_Msk << u32ChannelNum) ? 1 : 0);
000002  6980              LDR      r0,[r0,#0x18]
000004  2201              MOVS     r2,#1
000006  0492              LSLS     r2,r2,#18
000008  408a              LSLS     r2,r2,r1
00000a  4010              ANDS     r0,r0,r2
00000c  d000              BEQ      |L28.16|
00000e  2001              MOVS     r0,#1
                  |L28.16|
;;;564    }
000010  4770              BX       lr
;;;565    
                          ENDP

000012  0000              DCW      0x0000
                  |L28.20|
                          DCD      0x40040040

                          AREA ||i.PWM_GetDutyIntFlag||, CODE, READONLY, ALIGN=2

                  PWM_GetDutyIntFlag PROC
;;;368     */
;;;369    uint32_t PWM_GetDutyIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
000000  4804              LDR      r0,|L29.20|
;;;370    {
;;;371        return(PWM->INTSTS & (PWM_INTSTS_CMPDIF0_Msk << u32ChannelNum) ? 1 : 0);
000002  6980              LDR      r0,[r0,#0x18]
000004  22ff              MOVS     r2,#0xff
000006  3201              ADDS     r2,#1
000008  408a              LSLS     r2,r2,r1
00000a  4010              ANDS     r0,r0,r2
00000c  d000              BEQ      |L29.16|
00000e  2001              MOVS     r0,#1
                  |L29.16|
;;;372    }
000010  4770              BX       lr
;;;373    
                          ENDP

000012  0000              DCW      0x0000
                  |L29.20|
                          DCD      0x40040040

                          AREA ||i.PWM_GetFaultBrakeIntFlag||, CODE, READONLY, ALIGN=2

                  PWM_GetFaultBrakeIntFlag PROC
;;;510     */
;;;511    uint32_t PWM_GetFaultBrakeIntFlag (PWM_T *pwm, uint32_t u32BrakeSource)
000000  4802              LDR      r0,|L30.12|
;;;512    {
;;;513        return (PWM->INTSTS & u32BrakeSource ? 1 : 0);
000002  6980              LDR      r0,[r0,#0x18]
000004  4008              ANDS     r0,r0,r1
000006  d000              BEQ      |L30.10|
000008  2001              MOVS     r0,#1
                  |L30.10|
;;;514    }
00000a  4770              BX       lr
;;;515    
                          ENDP

                  |L30.12|
                          DCD      0x40040040

                          AREA ||i.PWM_GetPeriodIntFlag||, CODE, READONLY, ALIGN=2

                  PWM_GetPeriodIntFlag PROC
;;;414     */
;;;415    uint32_t PWM_GetPeriodIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
000000  4803              LDR      r0,|L31.16|
;;;416    {
;;;417        return(PWM->INTSTS & (PWM_INTSTS_ZIF0_Msk << u32ChannelNum) ? 1 : 0);
000002  6980              LDR      r0,[r0,#0x18]
000004  2201              MOVS     r2,#1
000006  408a              LSLS     r2,r2,r1
000008  4010              ANDS     r0,r0,r2
00000a  d000              BEQ      |L31.14|
00000c  2001              MOVS     r0,#1
                  |L31.14|
;;;418    }
00000e  4770              BX       lr
;;;419    
                          ENDP

                  |L31.16|
                          DCD      0x40040040

                          AREA ||i.PWM_GetRiseIntFlag||, CODE, READONLY, ALIGN=2

                  PWM_GetRiseIntFlag PROC
;;;460     */
;;;461    uint32_t PWM_GetRiseIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
000000  4804              LDR      r0,|L32.20|
;;;462    {
;;;463        return(PWM->INTSTS & (PWM_INTSTS_CMPUIF0_Msk << u32ChannelNum) ? 1 : 0);
000002  6980              LDR      r0,[r0,#0x18]
000004  2201              MOVS     r2,#1
000006  0612              LSLS     r2,r2,#24
000008  408a              LSLS     r2,r2,r1
00000a  4010              ANDS     r0,r0,r2
00000c  d000              BEQ      |L32.16|
00000e  2001              MOVS     r0,#1
                  |L32.16|
;;;464    }
000010  4770              BX       lr
;;;465    
                          ENDP

000012  0000              DCW      0x0000
                  |L32.20|
                          DCD      0x40040040

                          AREA ||i.PWM_Start||, CODE, READONLY, ALIGN=2

                  PWM_Start PROC
;;;108     */
;;;109    void PWM_Start (PWM_T *pwm, uint32_t u32ChannelMask)
000000  b530              PUSH     {r4,r5,lr}
;;;110    {
;;;111        uint32_t u32Mask = 0, i;
000002  2300              MOVS     r3,#0
;;;112        for(i = 0; i < PWM_CHANNEL_NUM; i ++) {
000004  461a              MOV      r2,r3
;;;113            if(u32ChannelMask & (1 << i)) {
000006  2001              MOVS     r0,#1
                  |L33.8|
000008  4604              MOV      r4,r0
00000a  4094              LSLS     r4,r4,r2
00000c  420c              TST      r4,r1
00000e  d003              BEQ      |L33.24|
000010  0095              LSLS     r5,r2,#2
000012  4604              MOV      r4,r0
;;;114                u32Mask |= (PWM_CTL_CNTEN0_Msk << (i * 4));
000014  40ac              LSLS     r4,r4,r5
000016  4323              ORRS     r3,r3,r4
                  |L33.24|
000018  1c52              ADDS     r2,r2,#1
00001a  2a06              CMP      r2,#6                 ;112
00001c  d3f4              BCC      |L33.8|
;;;115            }
;;;116        }
;;;117    
;;;118        PWM->CTL |= u32Mask;
00001e  4802              LDR      r0,|L33.40|
000020  6881              LDR      r1,[r0,#8]
000022  4319              ORRS     r1,r1,r3
000024  6081              STR      r1,[r0,#8]
;;;119    }
000026  bd30              POP      {r4,r5,pc}
;;;120    
                          ENDP

                  |L33.40|
                          DCD      0x40040000

                          AREA ||i.PWM_Stop||, CODE, READONLY, ALIGN=1

                  PWM_Stop PROC
;;;127     */
;;;128    void PWM_Stop (PWM_T *pwm, uint32_t u32ChannelMask)
000000  b530              PUSH     {r4,r5,lr}
;;;129    {
;;;130        uint32_t i;
;;;131        for(i = 0; i < PWM_CHANNEL_NUM; i ++) {
000002  2200              MOVS     r2,#0
;;;132            if(u32ChannelMask & (1 << i)) {
000004  2501              MOVS     r5,#1
000006  4614              MOV      r4,r2
                  |L34.8|
000008  462b              MOV      r3,r5
00000a  4093              LSLS     r3,r3,r2
00000c  420b              TST      r3,r1
00000e  d002              BEQ      |L34.22|
000010  0093              LSLS     r3,r2,#2
;;;133                *((__IO uint32_t *)((((uint32_t) & ((pwm)->PERIOD0)) + (i) * 4))) = 0;
000012  181b              ADDS     r3,r3,r0
000014  60dc              STR      r4,[r3,#0xc]
                  |L34.22|
000016  1c52              ADDS     r2,r2,#1
000018  2a06              CMP      r2,#6                 ;131
00001a  d3f5              BCC      |L34.8|
;;;134            }
;;;135        }
;;;136    
;;;137    }
00001c  bd30              POP      {r4,r5,pc}
;;;138    
                          ENDP


;*** Start embedded assembler ***

#line 1 "..\\..\\..\\Library\\StdDriver\\src\\pwm.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___5_pwm_c_03ee09af____REV16|
#line 388 "..\\..\\..\\Library\\CMSIS\\Include\\cmsis_armcc.h"
|__asm___5_pwm_c_03ee09af____REV16| PROC
#line 389

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___5_pwm_c_03ee09af____REVSH|
#line 402
|__asm___5_pwm_c_03ee09af____REVSH| PROC
#line 403

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
