; generated by Component: ARM Compiler 5.06 update 4 (build 422) Tool: ArmCC [4d3604]
; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o.\obj\main.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\main.d --cpu=Cortex-M0 --apcs=interwork -O3 --diag_suppress=9931 -I..\..\..\Library\CMSIS\Include -I..\..\..\Library\Device\Nuvoton\Mini58Series\Include -I..\..\..\Library\StdDriver\inc -I..\..\Template -I..\..\..\Library\StdDriver\driver -I.\RTE\_Template -ID:\Keil_v5\ARM\PACK\Nuvoton\NuMicro_DFP\1.0.9\Device\Mini58\Include -ID:\Keil_v5\ARM\CMSIS\Include -D__MICROLIB -D__UVISION_VERSION=523 --omf_browse=.\obj\main.crf ..\main.c]
                          THUMB

                          AREA ||i.SYS_Init||, CODE, READONLY, ALIGN=2

                  SYS_Init PROC
;;;26     
;;;27     void SYS_Init(void)
000000  b570              PUSH     {r4-r6,lr}
000002  2259              MOVS     r2,#0x59
000004  4c17              LDR      r4,|L1.100|
000006  2016              MOVS     r0,#0x16
000008  2188              MOVS     r1,#0x88
                  |L1.10|
00000a  6022              STR      r2,[r4,#0]
00000c  6020              STR      r0,[r4,#0]
00000e  6021              STR      r1,[r4,#0]
000010  6823              LDR      r3,[r4,#0]
000012  2b00              CMP      r3,#0
000014  d0f9              BEQ      |L1.10|
;;;28     {
;;;29         /* Unlock protected registers */
;;;30         SYS_UnlockReg();
;;;31     
;;;32     		/* Enable external 12MHz XTAL, HIRC */
;;;33         CLK->PWRCTL =  CLK_PWRCTL_HIRCEN_Msk;
000016  4914              LDR      r1,|L1.104|
000018  2004              MOVS     r0,#4
00001a  6008              STR      r0,[r1,#0]
;;;34     
;;;35         /* Enable HIRC clock (Internal RC 22.1184MHz) */
;;;36         CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
00001c  f7fffffe          BL       CLK_EnableXtalRC
;;;37         
;;;38         /* Wait for HIRC clock ready */
;;;39         CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
000020  2010              MOVS     r0,#0x10
000022  f7fffffe          BL       CLK_WaitClockReady
;;;40     
;;;41         /* Switch HCLK clock source to XTL */
;;;42         CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC,CLK_CLKDIV_HCLK(1));
000026  2100              MOVS     r1,#0
000028  2007              MOVS     r0,#7
00002a  f7fffffe          BL       CLK_SetHCLK
;;;43     		CLK_SetCoreClock(50000000U);
00002e  480f              LDR      r0,|L1.108|
000030  f7fffffe          BL       CLK_SetCoreClock
;;;44     
;;;45     //    /* STCLK to XTL STCLK to XTL */
;;;46     //    CLK_SetSysTickClockSrc(CLK_CLKSEL0_HCLKSEL_HIRC);
;;;47     
;;;48     		
;;;49         // Enable module clock
;;;50             CLK_EnableModuleClock(UART0_MODULE);
000034  480e              LDR      r0,|L1.112|
000036  f7fffffe          BL       CLK_EnableModuleClock
;;;51     		//CLK_EnableModuleClock(UART1_MODULE);
;;;52     		CLK_EnableModuleClock(ADC_MODULE);
00003a  4d0e              LDR      r5,|L1.116|
00003c  4628              MOV      r0,r5
00003e  f7fffffe          BL       CLK_EnableModuleClock
;;;53     		CLK_SetModuleClock(ADC_MODULE,CLK_CLKSEL1_ADCSEL_HCLK,CLK_CLKDIV_ADC(6));
000042  2205              MOVS     r2,#5
000044  0412              LSLS     r2,r2,#16
000046  2108              MOVS     r1,#8
000048  4628              MOV      r0,r5
00004a  f7fffffe          BL       CLK_SetModuleClock
;;;54     		CLK_EnableModuleClock(PWMCH01_MODULE);
00004e  480a              LDR      r0,|L1.120|
000050  f7fffffe          BL       CLK_EnableModuleClock
;;;55     		CLK_EnableModuleClock(PWMCH23_MODULE);
000054  4809              LDR      r0,|L1.124|
000056  f7fffffe          BL       CLK_EnableModuleClock
;;;56     		
;;;57         /* Update System Core Clock */
;;;58         /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock and cyclesPerUs automatically. */
;;;59         SystemCoreClockUpdate();
00005a  f7fffffe          BL       SystemCoreClockUpdate
00005e  2000              MOVS     r0,#0
000060  6020              STR      r0,[r4,#0]
;;;60     
;;;61     
;;;62         /* Lock protected registers */
;;;63     		SYS_LockReg();
;;;64     		
;;;65     
;;;66     }
000062  bd70              POP      {r4-r6,pc}
;;;67     
                          ENDP

                  |L1.100|
                          DCD      0x50000100
                  |L1.104|
                          DCD      0x50000200
                  |L1.108|
                          DCD      0x02faf080
                  |L1.112|
                          DCD      0xa7803d10
                  |L1.116|
                          DCD      0xa623fe1c
                  |L1.120|
                          DCD      0xa7c00014
                  |L1.124|
                          DCD      0xa7e00015

                          AREA ||i.main||, CODE, READONLY, ALIGN=2

                  main PROC
;;;69     uint8_t somtingtest[2] = {0x12,0x32};
;;;70     int main()
000000  f7fffffe          BL       SYS_Init
;;;71     {
;;;72     		SYS_Init();
;;;73     		iic_pan159_init();
000004  f7fffffe          BL       iic_pan159_init
;;;74             uart_init_pan159();
000008  f7fffffe          BL       uart_init_pan159
;;;75             printf("adc value is");
00000c  a00b              ADR      r0,|L2.60|
00000e  f7fffffe          BL       __2printf
;;;76     		rfspi_pan159_init();
000012  f7fffffe          BL       rfspi_pan159_init
;;;77     		pwm_pan159_init(12000);
000016  480d              LDR      r0,|L2.76|
000018  f7fffffe          BL       pwm_pan159_init
;;;78     		adc_pan159_init();
00001c  f7fffffe          BL       adc_pan159_init
;;;79     		rf_init();
000020  f7fffffe          BL       rf_init
;;;80             
;;;81         while(1){
;;;82                 adc_pan159_samp1(adc2_value);
;;;83                 //uart_send(somtingtest,1);
;;;84                 //printf("adc value is");
;;;85                 delay_ms(50);
000024  4d0a              LDR      r5,|L2.80|
000026  2631              MOVS     r6,#0x31              ;81
                  |L2.40|
000028  480a              LDR      r0,|L2.84|
00002a  f7fffffe          BL       adc_pan159_samp1
00002e  4634              MOV      r4,r6                 ;81
                  |L2.48|
000030  4628              MOV      r0,r5
000032  f7fffffe          BL       __delay_pan159
000036  1e64              SUBS     r4,r4,#1
000038  d2fa              BCS      |L2.48|
00003a  e7f5              B        |L2.40|
;;;86     		}
;;;87     
;;;88     }
;;;89     
                          ENDP

                  |L2.60|
00003c  61646320          DCB      "adc value is",0
000040  76616c75
000044  65206973
000048  00      
000049  00                DCB      0
00004a  00                DCB      0
00004b  00                DCB      0
                  |L2.76|
                          DCD      0x00002ee0
                  |L2.80|
                          DCD      0x00023238
                  |L2.84|
                          DCD      ||area_number.6||

                          AREA ||.data||, DATA, ALIGN=0

                  somtingtest
000000  1232              DCB      0x12,0x32

                          AREA ||area_number.6||, DATA, ALIGN=1

                          EXPORTAS ||area_number.6||, ||.data||
                  adc2_value
                          DCDU     0x00000000

;*** Start embedded assembler ***

#line 1 "..\\main.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___6_main_c_SYS_Init____REV16|
#line 388 "..\\..\\..\\Library\\CMSIS\\Include\\cmsis_armcc.h"
|__asm___6_main_c_SYS_Init____REV16| PROC
#line 389

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___6_main_c_SYS_Init____REVSH|
#line 402
|__asm___6_main_c_SYS_Init____REVSH| PROC
#line 403

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***

                  __ARM_use_no_argv EQU 0
