; generated by Component: ARM Compiler 5.06 update 4 (build 422) Tool: ArmCC [4d3604]
; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o.\obj\lib_driver_iic_pan159.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\lib_driver_iic_pan159.d --cpu=Cortex-M0 --apcs=interwork -O3 --diag_suppress=9931 -I..\..\..\Library\CMSIS\Include -I..\..\..\Library\Device\Nuvoton\Mini58Series\Include -I..\..\..\Library\StdDriver\inc -I..\..\Template -I..\..\..\Library\StdDriver\driver -I.\RTE\_Template -ID:\Keil_v5\ARM\PACK\Nuvoton\NuMicro_DFP\1.0.9\Device\Mini58\Include -ID:\Keil_v5\ARM\CMSIS\Include -D__MICROLIB -D__UVISION_VERSION=523 --omf_browse=.\obj\lib_driver_iic_pan159.crf ..\..\..\Library\StdDriver\driver\lib_driver_iic_pan159.c]
                          THUMB

                          AREA ||i.I2C0_IRQHandler||, CODE, READONLY, ALIGN=2

                  I2C0_IRQHandler PROC
;;;29     /*---------------------------------------------------------------------------------------------------------*/
;;;30     void I2C0_IRQHandler(void)
000000  b570              PUSH     {r4-r6,lr}
;;;31     {
;;;32         uint32_t u32Status;
;;;33     
;;;34         u32Status = I2C_GET_STATUS(I2C0);
000002  480a              LDR      r0,|L1.44|
000004  68c5              LDR      r5,[r0,#0xc]
;;;35     
;;;36         if (I2C_GET_TIMEOUT_FLAG(I2C0)) {
000006  6941              LDR      r1,[r0,#0x14]
000008  43c9              MVNS     r1,r1
00000a  07c9              LSLS     r1,r1,#31
00000c  d00a              BEQ      |L1.36|
;;;37             /* Clear I2C Timeout Flag */
;;;38             I2C_ClearTimeoutFlag(I2C0);
;;;39         } 
;;;40         else {
;;;41             if (s_I2CHandlerFn != NULL)
00000e  4c08              LDR      r4,|L1.48|
000010  68a0              LDR      r0,[r4,#8]  ; s_I2CHandlerFn
000012  2800              CMP      r0,#0
000014  d005              BEQ      |L1.34|
;;;42                 s_I2CHandlerFn(u32Status,buf_addr,cbk_success,cbk_failed);
000016  6923              LDR      r3,[r4,#0x10]  ; cbk_failed
000018  68e2              LDR      r2,[r4,#0xc]  ; cbk_success
00001a  6961              LDR      r1,[r4,#0x14]  ; buf_addr
00001c  68a4              LDR      r4,[r4,#8]  ; s_I2CHandlerFn
00001e  4628              MOV      r0,r5
000020  47a0              BLX      r4
                  |L1.34|
;;;43         }
;;;44     }
000022  bd70              POP      {r4-r6,pc}
                  |L1.36|
000024  f7fffffe          BL       I2C_ClearTimeoutFlag
000028  bd70              POP      {r4-r6,pc}
;;;45     
                          ENDP

00002a  0000              DCW      0x0000
                  |L1.44|
                          DCD      0x40020000
                  |L1.48|
                          DCD      ||.data||

                          AREA ||i.iic_master_rx||, CODE, READONLY, ALIGN=2

                  iic_master_rx PROC
;;;96     }
;;;97     void iic_master_rx(uint32_t u32Status ,uint8_t *buf,TCallback cbk, TCallback fail_cbk){
000000  b4f0              PUSH     {r4-r7}
;;;98         if (u32Status == 0x08) {                    /* START has been transmitted and prepare SLA+W */
;;;99             I2C_SET_DATA(I2C0, g_u8DeviceAddr << 1);     /* Write SLA+W to Register I2CDAT */
000002  4d27              LDR      r5,|L2.160|
000004  4c25              LDR      r4,|L2.156|
000006  786f              LDRB     r7,[r5,#1]
;;;100            I2C_SET_CONTROL_REG(I2C0, I2C_SI);
000008  263c              MOVS     r6,#0x3c
00000a  007f              LSLS     r7,r7,#1              ;99
00000c  2808              CMP      r0,#8                 ;98
00000e  d011              BEQ      |L2.52|
;;;101        } 
;;;102        else if (u32Status == 0x18) {             /* SLA+W has been transmitted and ACK has been received */
000010  2818              CMP      r0,#0x18
000012  d011              BEQ      |L2.56|
;;;103            I2C_SET_DATA(I2C0, g_u8RegAddr);
;;;104            I2C_SET_CONTROL_REG(I2C0, I2C_SI);
;;;105        } 
;;;106        else if (u32Status == 0x20) {             /* SLA+W has been transmitted and NACK has been received */
000014  2820              CMP      r0,#0x20
000016  d015              BEQ      |L2.68|
;;;107            I2C_SET_CONTROL_REG(I2C0, I2C_STO | I2C_SI);
;;;108        } 
;;;109        else if (u32Status == 0x28) {             /* DATA has been transmitted and ACK has been received */
000018  2828              CMP      r0,#0x28
00001a  d017              BEQ      |L2.76|
;;;110            I2C_SET_CONTROL_REG(I2C0, I2C_STA | I2C_SI);
;;;111        } 
;;;112        else if (u32Status == 0x10) {             /* Repeat START has been transmitted and prepare SLA+R */
00001c  2810              CMP      r0,#0x10
00001e  d019              BEQ      |L2.84|
;;;113            I2C_SET_DATA(I2C0, ((g_u8DeviceAddr << 1) | 0x01));   /* Write SLA+R to Register I2CDAT */
;;;114            I2C_SET_CONTROL_REG(I2C0, I2C_SI);
;;;115        } 
;;;116        else if (u32Status == 0x40) {             /* SLA+R has been transmitted and ACK has been received */
000020  2840              CMP      r0,#0x40
000022  d019              BEQ      |L2.88|
000024  462f              MOV      r7,r5                 ;99
;;;117            I2C_SET_CONTROL_REG(I2C0, I2C_SI | I2C_AA );
;;;118        } 
;;;119        else if (u32Status == 0x50) {             /* DATA has been received and ACK has been returned */
;;;120            if(g_u8DataLen != g_u8DataLenMax-2){
000026  78ff              LDRB     r7,[r7,#3]
000028  2850              CMP      r0,#0x50              ;119
00002a  d019              BEQ      |L2.96|
;;;121                buf[g_u8DataLen++] = I2C_GET_DATA(I2C0);
;;;122                I2C_SET_CONTROL_REG(I2C0, I2C_SI | I2C_AA);
;;;123            }
;;;124            else{
;;;125                buf[g_u8DataLen++] = I2C_GET_DATA(I2C0);
;;;126                I2C_SET_CONTROL_REG(I2C0, I2C_SI );
;;;127            }
;;;128        } 
;;;129        else if (u32Status == 0x58) {             /* DATA has been received and NACK has been returned */
00002c  2858              CMP      r0,#0x58
00002e  d027              BEQ      |L2.128|
;;;130                buf[g_u8DataLen++] = I2C_GET_DATA(I2C0);
;;;131                I2C_SET_CONTROL_REG(I2C0, I2C_STO | I2C_SI);
;;;132                g_u8EndFlag = 1;
;;;133                cbk();
;;;134        } 
;;;135        else {
;;;136            fail_cbk();
000030  bcf0              POP      {r4-r7}
000032  4718              BX       r3
                  |L2.52|
000034  60a7              STR      r7,[r4,#8]            ;99
000036  e01f              B        |L2.120|
                  |L2.56|
000038  78a8              LDRB     r0,[r5,#2]            ;103  ; g_u8RegAddr
00003a  60a0              STR      r0,[r4,#8]            ;103
00003c  e01c              B        |L2.120|
                  |L2.62|
00003e  6020              STR      r0,[r4,#0]            ;100
;;;137            /* TO DO */
;;;138            //printf("Status 0x%x is NOT processed\n", u32Status);
;;;139        }
;;;140    }
000040  bcf0              POP      {r4-r7}
000042  4770              BX       lr
                  |L2.68|
000044  6820              LDR      r0,[r4,#0]            ;107
000046  43b0              BICS     r0,r0,r6              ;107
000048  3018              ADDS     r0,r0,#0x18           ;107
00004a  e7f8              B        |L2.62|
                  |L2.76|
00004c  6820              LDR      r0,[r4,#0]            ;110
00004e  43b0              BICS     r0,r0,r6              ;110
000050  3028              ADDS     r0,r0,#0x28           ;110
000052  e7f4              B        |L2.62|
                  |L2.84|
000054  1c7f              ADDS     r7,r7,#1              ;110
000056  e7ed              B        |L2.52|
                  |L2.88|
000058  6820              LDR      r0,[r4,#0]            ;117
00005a  43b0              BICS     r0,r0,r6              ;117
00005c  300c              ADDS     r0,r0,#0xc            ;117
00005e  e7ee              B        |L2.62|
                  |L2.96|
000060  7928              LDRB     r0,[r5,#4]            ;120  ; g_u8DataLenMax
000062  1e80              SUBS     r0,r0,#2              ;120
000064  4287              CMP      r7,r0                 ;120
000066  68a0              LDR      r0,[r4,#8]            ;125
000068  55c8              STRB     r0,[r1,r7]            ;125
00006a  78e8              LDRB     r0,[r5,#3]            ;125  ; g_u8DataLen
00006c  d002              BEQ      |L2.116|
00006e  1c40              ADDS     r0,r0,#1              ;120
000070  70e8              STRB     r0,[r5,#3]            ;121
000072  e7f1              B        |L2.88|
                  |L2.116|
000074  1c40              ADDS     r0,r0,#1              ;122
000076  70e8              STRB     r0,[r5,#3]            ;125
                  |L2.120|
000078  6820              LDR      r0,[r4,#0]            ;126
00007a  43b0              BICS     r0,r0,r6              ;126
00007c  3008              ADDS     r0,r0,#8              ;126
00007e  e7de              B        |L2.62|
                  |L2.128|
000080  68a0              LDR      r0,[r4,#8]            ;130
000082  55c8              STRB     r0,[r1,r7]            ;130
000084  78e8              LDRB     r0,[r5,#3]            ;130  ; g_u8DataLen
000086  1c40              ADDS     r0,r0,#1              ;130
000088  70e8              STRB     r0,[r5,#3]            ;130
00008a  6820              LDR      r0,[r4,#0]            ;131
00008c  43b0              BICS     r0,r0,r6              ;131
00008e  3018              ADDS     r0,r0,#0x18           ;131
000090  6020              STR      r0,[r4,#0]            ;131
000092  2001              MOVS     r0,#1                 ;132
000094  7028              STRB     r0,[r5,#0]            ;132
000096  bcf0              POP      {r4-r7}               ;133
000098  4710              BX       r2                    ;133
;;;141    
                          ENDP

00009a  0000              DCW      0x0000
                  |L2.156|
                          DCD      0x40020000
                  |L2.160|
                          DCD      ||.data||

                          AREA ||i.iic_master_tx||, CODE, READONLY, ALIGN=2

                  iic_master_tx PROC
;;;67     
;;;68     void iic_master_tx(uint32_t u32Status ,uint8_t *buf, TCallback cbk, TCallback fail_cbk)
000000  b4f0              PUSH     {r4-r7}
;;;69     {
;;;70         if (u32Status == 0x08) {                    /* START has been transmitted */
;;;71             I2C_SET_DATA(I2C0, g_u8DeviceAddr << 1);     /* Write SLA+W to Register I2CDAT */
000002  4c16              LDR      r4,|L3.92|
;;;72             I2C_SET_CONTROL_REG(I2C0, I2C_SI);
000004  263c              MOVS     r6,#0x3c
000006  4d16              LDR      r5,|L3.96|
000008  2808              CMP      r0,#8                 ;70
00000a  d007              BEQ      |L3.28|
;;;73         } 
;;;74         else if (u32Status == 0x18) {             /* SLA+W has been transmitted and ACK has been received */
00000c  2818              CMP      r0,#0x18
00000e  d008              BEQ      |L3.34|
;;;75             I2C_SET_DATA(I2C0, g_u8RegAddr);
;;;76             I2C_SET_CONTROL_REG(I2C0, I2C_SI);
;;;77         } 
;;;78         else if (u32Status == 0x20) {             /* SLA+W has been transmitted and NACK has been received */
000010  2820              CMP      r0,#0x20
000012  d00e              BEQ      |L3.50|
;;;79             I2C_SET_CONTROL_REG(I2C0, I2C_STO | I2C_SI);
;;;80         } 
;;;81         else if (u32Status == 0x28) {             /* DATA has been transmitted and ACK has been received */
000014  2828              CMP      r0,#0x28
000016  d010              BEQ      |L3.58|
;;;82             if (g_u8DataLen != g_u8DataLenMax) {
;;;83                 I2C_SET_DATA(I2C0, buf[g_u8DataLen++]);
;;;84                 I2C_SET_CONTROL_REG(I2C0, I2C_SI);
;;;85             } else {
;;;86                 I2C_SET_CONTROL_REG(I2C0, I2C_STO | I2C_SI);
;;;87                 g_u8EndFlag = 1;
;;;88                 cbk();
;;;89             }
;;;90         } 
;;;91         else {
;;;92             fail_cbk();
000018  bcf0              POP      {r4-r7}
00001a  4718              BX       r3
                  |L3.28|
00001c  7868              LDRB     r0,[r5,#1]            ;71  ; g_u8DeviceAddr
00001e  0040              LSLS     r0,r0,#1              ;71
000020  e000              B        |L3.36|
                  |L3.34|
000022  78a8              LDRB     r0,[r5,#2]            ;75  ; g_u8RegAddr
                  |L3.36|
000024  60a0              STR      r0,[r4,#8]            ;71
                  |L3.38|
000026  6820              LDR      r0,[r4,#0]            ;84
000028  43b0              BICS     r0,r0,r6              ;84
00002a  3008              ADDS     r0,r0,#8              ;84
                  |L3.44|
00002c  6020              STR      r0,[r4,#0]            ;72
;;;93             /* TO DO */
;;;94     //        printf("Status 0x%x is NOT processed\n", u32Status);
;;;95         }
;;;96     }
00002e  bcf0              POP      {r4-r7}
000030  4770              BX       lr
                  |L3.50|
000032  6820              LDR      r0,[r4,#0]            ;79
000034  43b0              BICS     r0,r0,r6              ;79
000036  3018              ADDS     r0,r0,#0x18           ;79
000038  e7f8              B        |L3.44|
                  |L3.58|
00003a  78e8              LDRB     r0,[r5,#3]            ;82  ; g_u8DataLen
00003c  792b              LDRB     r3,[r5,#4]            ;82  ; g_u8DataLenMax
00003e  4298              CMP      r0,r3                 ;82
000040  d004              BEQ      |L3.76|
000042  5c09              LDRB     r1,[r1,r0]            ;83
000044  60a1              STR      r1,[r4,#8]            ;83
000046  1c40              ADDS     r0,r0,#1              ;83
000048  70e8              STRB     r0,[r5,#3]            ;83
00004a  e7ec              B        |L3.38|
                  |L3.76|
00004c  6820              LDR      r0,[r4,#0]            ;86
00004e  43b0              BICS     r0,r0,r6              ;86
000050  3018              ADDS     r0,r0,#0x18           ;86
000052  6020              STR      r0,[r4,#0]            ;86
000054  2001              MOVS     r0,#1                 ;87
000056  7028              STRB     r0,[r5,#0]            ;87
000058  bcf0              POP      {r4-r7}               ;88
00005a  4710              BX       r2                    ;88
;;;97     void iic_master_rx(uint32_t u32Status ,uint8_t *buf,TCallback cbk, TCallback fail_cbk){
                          ENDP

                  |L3.92|
                          DCD      0x40020000
                  |L3.96|
                          DCD      ||.data||

                          AREA ||i.iic_pan159_init||, CODE, READONLY, ALIGN=2

                  iic_pan159_init PROC
;;;45     
;;;46     void iic_pan159_init(void)
000000  b510              PUSH     {r4,lr}
;;;47     {
;;;48         uint32_t u32Div;
;;;49     
;;;50         CLK_EnableModuleClock(I2C0_MODULE);
000002  481c              LDR      r0,|L4.116|
000004  f7fffffe          BL       CLK_EnableModuleClock
;;;51         SYS->P3_MFP &= ~SYS_MFP_P34_Msk;
000008  2005              MOVS     r0,#5
00000a  0700              LSLS     r0,r0,#28
00000c  6bc1              LDR      r1,[r0,#0x3c]
00000e  4a1a              LDR      r2,|L4.120|
000010  4011              ANDS     r1,r1,r2
000012  63c1              STR      r1,[r0,#0x3c]
;;;52         SYS->P3_MFP |= SYS_MFP_P34_I2C0_SDA;
000014  6bc1              LDR      r1,[r0,#0x3c]
000016  2201              MOVS     r2,#1
000018  0312              LSLS     r2,r2,#12
00001a  4311              ORRS     r1,r1,r2
00001c  63c1              STR      r1,[r0,#0x3c]
;;;53         SYS->P3_MFP &= ~SYS_MFP_P35_Msk;
00001e  6bc1              LDR      r1,[r0,#0x3c]
000020  4a16              LDR      r2,|L4.124|
000022  4011              ANDS     r1,r1,r2
000024  63c1              STR      r1,[r0,#0x3c]
;;;54         SYS->P3_MFP |= SYS_MFP_P35_I2C0_SCL;
000026  6bc1              LDR      r1,[r0,#0x3c]
000028  2201              MOVS     r2,#1
00002a  0352              LSLS     r2,r2,#13
00002c  4311              ORRS     r1,r1,r2
00002e  63c1              STR      r1,[r0,#0x3c]
;;;55         
;;;56         SYS->IPRST1 |= SYS_IPRST1_I2C0RST_Msk;
000030  68c2              LDR      r2,[r0,#0xc]
000032  21ff              MOVS     r1,#0xff
000034  3101              ADDS     r1,#1
000036  430a              ORRS     r2,r2,r1
000038  60c2              STR      r2,[r0,#0xc]
;;;57         SYS->IPRST1 &= ~SYS_IPRST1_I2C0RST_Msk;
00003a  68c2              LDR      r2,[r0,#0xc]
00003c  438a              BICS     r2,r2,r1
00003e  60c2              STR      r2,[r0,#0xc]
;;;58         
;;;59         u32Div = (uint32_t) (((SystemCoreClock * 10)/(400000 * 4) + 5) / 10 - 1); /* Compute proper divider for I2C clock */
000040  480f              LDR      r0,|L4.128|
000042  210a              MOVS     r1,#0xa
000044  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
000046  4348              MULS     r0,r1,r0
000048  490e              LDR      r1,|L4.132|
00004a  f7fffffe          BL       __aeabi_uidivmod
00004e  210a              MOVS     r1,#0xa
000050  1d40              ADDS     r0,r0,#5
000052  f7fffffe          BL       __aeabi_uidivmod
;;;60         I2C0->CLKDIV = u32Div;
000056  490c              LDR      r1,|L4.136|
000058  1e40              SUBS     r0,r0,#1
00005a  6108              STR      r0,[r1,#0x10]
;;;61         I2C0->CTL |= I2C_CTL_I2CEN_Msk;
00005c  6808              LDR      r0,[r1,#0]
00005e  2240              MOVS     r2,#0x40
000060  4310              ORRS     r0,r0,r2
000062  6008              STR      r0,[r1,#0]
;;;62         
;;;63         I2C0->CTL |= I2C_CTL_INTEN_Msk;
000064  6808              LDR      r0,[r1,#0]
000066  2280              MOVS     r2,#0x80
000068  4310              ORRS     r0,r0,r2
00006a  6008              STR      r0,[r1,#0]
00006c  4907              LDR      r1,|L4.140|
00006e  02d0              LSLS     r0,r2,#11
000070  6008              STR      r0,[r1,#0]
;;;64         NVIC_EnableIRQ(I2C0_IRQn);
;;;65         
;;;66     }
000072  bd10              POP      {r4,pc}
;;;67     
                          ENDP

                  |L4.116|
                          DCD      0x80000008
                  |L4.120|
                          DCD      0xffffefef
                  |L4.124|
                          DCD      0xffffdfdf
                  |L4.128|
                          DCD      SystemCoreClock
                  |L4.132|
                          DCD      0x00186a00
                  |L4.136|
                          DCD      0x40020000
                  |L4.140|
                          DCD      0xe000e100

                          AREA ||i.iic_start_read_bytes||, CODE, READONLY, ALIGN=2

                  iic_start_read_bytes PROC
;;;161    
;;;162    void iic_start_read_bytes(uint16_t devAddr,uint8_t regAddr, uint8_t *buf, uint8_t len,TCallback cbk, TCallback fail_cbk)
000000  b570              PUSH     {r4-r6,lr}
;;;163    {
;;;164        g_u8DataLenMax = len;
000002  4c0b              LDR      r4,|L5.48|
000004  9e05              LDR      r6,[sp,#0x14]
000006  9d04              LDR      r5,[sp,#0x10]
000008  7123              STRB     r3,[r4,#4]
;;;165        g_u8DeviceAddr = devAddr;
00000a  7060              STRB     r0,[r4,#1]
;;;166        g_u8RegAddr = regAddr;
00000c  70a1              STRB     r1,[r4,#2]
;;;167        g_u8DataLen = 0;
00000e  2000              MOVS     r0,#0
000010  70e0              STRB     r0,[r4,#3]
;;;168        g_u8EndFlag = 0;
000012  7020              STRB     r0,[r4,#0]
;;;169        s_I2CHandlerFn = (I2C_FUNC)iic_master_rx;
000014  4807              LDR      r0,|L5.52|
000016  60a0              STR      r0,[r4,#8]  ; s_I2CHandlerFn
;;;170        cbk_success = cbk;
000018  60e5              STR      r5,[r4,#0xc]  ; cbk_success
;;;171        cbk_failed = fail_cbk;
00001a  6126              STR      r6,[r4,#0x10]  ; cbk_failed
;;;172        buf_addr = buf;
;;;173        //CLK_SysTickDelay(5000);
;;;174        /* I2C as master sends START signal */
;;;175        I2C_START(I2C0);
00001c  4906              LDR      r1,|L5.56|
00001e  6162              STR      r2,[r4,#0x14]  ; buf_addr
000020  6808              LDR      r0,[r1,#0]
000022  2208              MOVS     r2,#8
000024  4390              BICS     r0,r0,r2
000026  2220              MOVS     r2,#0x20
000028  4310              ORRS     r0,r0,r2
00002a  6008              STR      r0,[r1,#0]
;;;176         //while (g_u8EndFlag == 0);
;;;177    }
00002c  bd70              POP      {r4-r6,pc}
;;;178    
                          ENDP

00002e  0000              DCW      0x0000
                  |L5.48|
                          DCD      ||.data||
                  |L5.52|
                          DCD      iic_master_rx
                  |L5.56|
                          DCD      0x40020000

                          AREA ||i.iic_start_send_bytes||, CODE, READONLY, ALIGN=2

                  iic_start_send_bytes PROC
;;;141    
;;;142    void iic_start_send_bytes(uint16_t devAddr,uint8_t regAddr, uint8_t *buf, uint8_t len,TCallback cbk, TCallback fail_cbk)
000000  b570              PUSH     {r4-r6,lr}
;;;143    {
;;;144        g_u8DataLenMax = len;
000002  4c0b              LDR      r4,|L6.48|
000004  9e05              LDR      r6,[sp,#0x14]
000006  9d04              LDR      r5,[sp,#0x10]
000008  7123              STRB     r3,[r4,#4]
;;;145        g_u8DeviceAddr = devAddr;
00000a  7060              STRB     r0,[r4,#1]
;;;146        
;;;147        g_u8RegAddr = regAddr;
00000c  70a1              STRB     r1,[r4,#2]
;;;148    
;;;149        g_u8DataLen = 0;
00000e  2000              MOVS     r0,#0
000010  70e0              STRB     r0,[r4,#3]
;;;150        g_u8EndFlag = 0;
000012  7020              STRB     r0,[r4,#0]
;;;151        /* I2C function to write data to slave */
;;;152        s_I2CHandlerFn = (I2C_FUNC)iic_master_tx;
000014  4807              LDR      r0,|L6.52|
000016  60a0              STR      r0,[r4,#8]  ; s_I2CHandlerFn
;;;153        cbk_success = cbk;
000018  60e5              STR      r5,[r4,#0xc]  ; cbk_success
;;;154        cbk_failed = fail_cbk;
00001a  6126              STR      r6,[r4,#0x10]  ; cbk_failed
;;;155        buf_addr = buf;
;;;156        /* I2C as master sends START signal */
;;;157        I2C_START(I2C0);
00001c  4906              LDR      r1,|L6.56|
00001e  6162              STR      r2,[r4,#0x14]  ; buf_addr
000020  6808              LDR      r0,[r1,#0]
000022  2208              MOVS     r2,#8
000024  4390              BICS     r0,r0,r2
000026  2220              MOVS     r2,#0x20
000028  4310              ORRS     r0,r0,r2
00002a  6008              STR      r0,[r1,#0]
;;;158       
;;;159    
;;;160    }
00002c  bd70              POP      {r4-r6,pc}
;;;161    
                          ENDP

00002e  0000              DCW      0x0000
                  |L6.48|
                          DCD      ||.data||
                  |L6.52|
                          DCD      iic_master_tx
                  |L6.56|
                          DCD      0x40020000

                          AREA ||i.is_iic_busy||, CODE, READONLY, ALIGN=2

                  is_iic_busy PROC
;;;178    
;;;179    uint8_t is_iic_busy(void)
000000  4803              LDR      r0,|L7.16|
;;;180    {
;;;181        if(g_u8EndFlag){
000002  7800              LDRB     r0,[r0,#0]  ; g_u8EndFlag
000004  2800              CMP      r0,#0
000006  d001              BEQ      |L7.12|
;;;182            return 0;
000008  2000              MOVS     r0,#0
;;;183        }
;;;184        else{
;;;185            return 1;
;;;186        }
;;;187    }
00000a  4770              BX       lr
                  |L7.12|
00000c  2001              MOVS     r0,#1                 ;185
00000e  4770              BX       lr
                          ENDP

                  |L7.16|
                          DCD      ||.data||

                          AREA ||.data||, DATA, ALIGN=2

                  g_u8EndFlag
000000  00                DCB      0x00
                  g_u8DeviceAddr
000001  00                DCB      0x00
                  g_u8RegAddr
000002  00                DCB      0x00
                  g_u8DataLen
000003  00                DCB      0x00
                  g_u8DataLenMax
000004  00000000          DCB      0x00,0x00,0x00,0x00
                  s_I2CHandlerFn
                          DCD      0x00000000
                  cbk_success
                          DCD      0x00000000
                  cbk_failed
                          DCD      0x00000000
                  buf_addr
                          DCD      0x00000000

;*** Start embedded assembler ***

#line 1 "..\\..\\..\\Library\\StdDriver\\driver\\lib_driver_iic_pan159.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___23_lib_driver_iic_pan159_c_ae965f01____REV16|
#line 388 "..\\..\\..\\Library\\CMSIS\\Include\\cmsis_armcc.h"
|__asm___23_lib_driver_iic_pan159_c_ae965f01____REV16| PROC
#line 389

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___23_lib_driver_iic_pan159_c_ae965f01____REVSH|
#line 402
|__asm___23_lib_driver_iic_pan159_c_ae965f01____REVSH| PROC
#line 403

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
